Orange Pi5 kernel

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 *
 */

/ {
	chosen: chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff690000 firmware_class.path=/system/vendor/firmware";
	};

	fiq_debugger: fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <0>;  /* If enable uart uses irq instead of fiq */
		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;   /* signal irq */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		drm_logo: drm-logo@00000000 {
			compatible = "rockchip,drm-logo";
			reg = <0x0 0x0 0x0 0x0>;
		};

		ramoops: ramoops@110000 {
			compatible = "ramoops";
			reg = <0x0 0x110000 0x0 0xf0000>;
			record-size = <0x20000>;
			console-size = <0x80000>;
			ftrace-size = <0x00000>;
			pmsg-size = <0x50000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x2000000>;
			linux,cma-default;
		};
	};

	ion {
		compatible = "rockchip,ion";
		#address-cells = <1>;
		#size-cells = <0>;

		cma-heap {
			reg = <0x00000000 0x2800000>;
		};

		system-heap {
		};
	};

	firmware {
		firmware_android: android {};

		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	rga@ff920000 {
		compatible = "rockchip,rga2";
		dev_mode = <1>;
		reg = <0x0 0xff920000 0x0 0x1000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		status = "okay";
	};
};

&cluster1_opp {
	rockchip,avs = <1>;
};

&display_subsystem {
	status = "okay";

	logo-memory-region = <&drm_logo>;
	route {
		route_dsi: route-dsi {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vop_out_dsi>;
		};

		route_edp: route-edp {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vop_out_edp>;
		};

		route_hdmi: route-hdmi {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vop_out_hdmi>;
		};

		route_lvds: route-lvds {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vop_out_lvds>;
		};

		route_rgb: route-rgb {
			status = "disabled";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "center";
			charge_logo,mode = "center";
			connect = <&vop_out_rgb>;
		};

	};
};

&dsi {
	panel@0 {
		reg = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				panel_in_dsi: endpoint {
					remote-endpoint = <&dsi_out_panel>;
				};
			};
		};
	};

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@1 {
			reg = <1>;

			dsi_out_panel: endpoint {
				remote-endpoint = <&panel_in_dsi>;
			};
		};
	};
};

&hevc {
	status = "okay";
};

&hevc_mmu {
	status = "okay";
};

&iep {
	status = "okay";
};

&iep_mmu {
	status = "okay";
};

&mailbox {
	status = "okay";
};

&mailbox_scpi {
	status = "okay";
};

&mpp_srv {
	status = "okay";
};

&vdpu {
	status = "okay";
};

&vepu {
	status = "okay";
};

&vpu_mmu {
	status = "okay";
};

&vop {
	support-multi-area;
	status = "okay";
};

&vop_mmu {
	status = "okay";
};

&isp {
	status = "okay";
};

&isp_mmu {
	status = "okay";
};

&cif {
	status = "okay";
};

&rng {
	status = "okay";
};

&vip_mmu {
	status = "okay";
};

&video_phy {
	status = "okay";
};

&usb_otg {
	status = "okay";
};

&pinctrl {
	isp {
		cif_clkout: cif-clkout {
			rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
		};

		isp_dvp_d2d9: isp-dvp-d2d9 {
			rockchip,pins =
					<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
					<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
					<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
					<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
					<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
					<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
					<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
					<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
					<1 RK_PB0 1 &pcfg_pull_none>,//cif_sync
					<1 RK_PB1 1 &pcfg_pull_none>,//cif_href
					<1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin
					<1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
		};

		isp_dvp_d0d1: isp-dvp-d0d1 {
			rockchip,pins =
					<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
					<1 RK_PB5 1 &pcfg_pull_none>;//cif_data1
		};

		isp_dvp_d10d11:isp_d10d11 {
			rockchip,pins =
					<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
					<1 RK_PB7 1 &pcfg_pull_none>;//cif_data11
		};

		isp_dvp_d0d7: isp-dvp-d0d7 {
			rockchip,pins =
					<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
					<1 RK_PB5 1 &pcfg_pull_none>,//cif_data1
					<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
					<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
					<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
					<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
					<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
					<1 RK_PA5 1 &pcfg_pull_none>;//cif_data7
		};

		isp_dvp_d4d11: isp-dvp-d4d11 {
			rockchip,pins =
					<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
					<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
					<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
					<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
					<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
					<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
					<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
					<1 RK_PC1 1 &pcfg_pull_none>;//cif_data11
		};

		isp_shutter: isp-shutter {
			rockchip,pins =
					<3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN
					<3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG
		};

		isp_flash_trigger: isp-flash-trigger {
			rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
		};

		isp_prelight: isp-prelight {
			rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
		};

		isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
		};
	};
};