^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/vfp/vfpinstr.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 ARM Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written by Deep Blue Solutions Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * VFP instruction masks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define INST_CPRT(inst) ((inst) & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define INST_CPRT_L(inst) ((inst) & (1 << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define INST_CPNUM(inst) ((inst) & 0xf00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPNUM(cp) ((cp) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FOP_MASK (0x00b00040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FOP_FMAC (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FOP_FNMAC (0x00000040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FOP_FMSC (0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FOP_FNMSC (0x00100040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FOP_FMUL (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FOP_FNMUL (0x00200040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FOP_FADD (0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FOP_FSUB (0x00300040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FOP_FDIV (0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FOP_EXT (0x00b00040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FEXT_MASK (0x000f0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FEXT_FCPY (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FEXT_FABS (0x00000080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FEXT_FNEG (0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FEXT_FSQRT (0x00010080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FEXT_FCMP (0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FEXT_FCMPE (0x00040080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FEXT_FCMPZ (0x00050000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FEXT_FCMPEZ (0x00050080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FEXT_FCVT (0x00070080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FEXT_FUITO (0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FEXT_FSITO (0x00080080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FEXT_FTOUI (0x000c0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FEXT_FTOUIZ (0x000c0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FEXT_FTOSI (0x000d0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FEXT_FTOSIZ (0x000d0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FPSCR_N (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FPSCR_Z (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FPSCR_C (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FPSCR_V (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef CONFIG_AS_VFP_VMRS_FPINST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define fmrx(_vfp_) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) asm(".fpu vfpv2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "vmrs %0, " #_vfp_ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) : "=r" (__v) : : "cc"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define fmxr(_vfp_,_var_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) asm(".fpu vfpv2\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "vmsr " #_vfp_ ", %0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) : : "r" (_var_) : "cc")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define vfpreg(_vfp_) #_vfp_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define fmrx(_vfp_) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) : "=r" (__v) : : "cc"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define fmxr(_vfp_,_var_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) : : "r" (_var_) : "cc")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 vfp_single_cpdo(u32 inst, u32 fpscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 vfp_double_cpdo(u32 inst, u32 fpscr);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags