Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/vfp/vfp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004 ARM Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Written by Deep Blue Solutions Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	if (shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 		if (shift < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 			val = val >> shift | ((val << (32 - shift)) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 			val = val != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	if (shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		if (shift < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 			val = val >> shift | ((val << (64 - shift)) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			val = val != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static inline u32 vfp_hi64to32jamming(u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	asm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	"cmp	%Q1, #1		@ vfp_hi64to32jamming\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	"movcc	%0, %R1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	"orrcs	%0, %R1, #1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	: "=r" (v) : "r" (val) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline void add128(u64 *resh, u64 *resl, u64 nh, u64 nl, u64 mh, u64 ml)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	asm(	"adds	%Q0, %Q2, %Q4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		"adcs	%R0, %R2, %R4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		"adcs	%Q1, %Q3, %Q5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		"adc	%R1, %R3, %R5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	    : "=r" (nl), "=r" (nh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	    : "0" (nl), "1" (nh), "r" (ml), "r" (mh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	    : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	*resh = nh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	*resl = nl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static inline void sub128(u64 *resh, u64 *resl, u64 nh, u64 nl, u64 mh, u64 ml)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	asm(	"subs	%Q0, %Q2, %Q4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		"sbcs	%R0, %R2, %R4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		"sbcs	%Q1, %Q3, %Q5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		"sbc	%R1, %R3, %R5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	    : "=r" (nl), "=r" (nh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	    : "0" (nl), "1" (nh), "r" (ml), "r" (mh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	    : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	*resh = nh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	*resl = nl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static inline void mul64to128(u64 *resh, u64 *resl, u64 n, u64 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 nh, nl, mh, ml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u64 rh, rma, rmb, rl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	nl = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ml = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	rl = (u64)nl * ml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	nh = n >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	rma = (u64)nh * ml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	mh = m >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	rmb = (u64)nl * mh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	rma += rmb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	rh = (u64)nh * mh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	rh += ((u64)(rma < rmb) << 32) + (rma >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	rma <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	rl += rma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	rh += (rl < rma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	*resl = rl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	*resh = rh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static inline void shift64left(u64 *resh, u64 *resl, u64 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	*resh = n >> 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	*resl = n << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline u64 vfp_hi64multiply64(u64 n, u64 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u64 rh, rl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mul64to128(&rh, &rl, n, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return rh | (rl != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u64 mh, ml, remh, reml, termh, terml, z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (nh >= m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return ~0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	mh = m >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (mh << 32 <= nh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		z = 0xffffffff00000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		z = nh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		do_div(z, mh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		z <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mul64to128(&termh, &terml, m, z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	sub128(&remh, &reml, nh, nl, termh, terml);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ml = m << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	while ((s64)remh < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		z -= 0x100000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		add128(&remh, &reml, remh, reml, mh, ml);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	remh = (remh << 32) | (reml >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (mh << 32 <= remh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		z |= 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		do_div(remh, mh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		z |= remh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * Operations on unpacked elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define vfp_sign_negate(sign)	(sign ^ 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * Single-precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct vfp_single {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	s16	exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u16	sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32	significand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) asmlinkage s32 vfp_get_float(unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) asmlinkage void vfp_put_float(s32 val, unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * VFP_SINGLE_LOW_BITS - number of low bits in the unpacked significand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *  which are not propagated to the float upon packing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VFP_SINGLE_MANTISSA_BITS	(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VFP_SINGLE_EXPONENT_BITS	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VFP_SINGLE_LOW_BITS		(32 - VFP_SINGLE_MANTISSA_BITS - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VFP_SINGLE_LOW_BITS_MASK	((1 << VFP_SINGLE_LOW_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * The bit in an unpacked float which indicates that it is a quiet NaN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VFP_SINGLE_SIGNIFICAND_QNAN	(1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * Operations on packed single-precision numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define vfp_single_packed_sign(v)	((v) & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define vfp_single_packed_negate(v)	((v) ^ 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define vfp_single_packed_abs(v)	((v) & ~0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define vfp_single_packed_exponent(v)	(((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define vfp_single_packed_mantissa(v)	((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  * Unpack a single-precision float.  Note that this returns the magnitude
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * of the single-precision float mantissa with the 1. if necessary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * aligned to bit 30.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline void vfp_single_unpack(struct vfp_single *s, s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 significand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	s->sign = vfp_single_packed_sign(val) >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	s->exponent = vfp_single_packed_exponent(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	significand = (u32) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	significand = (significand << (32 - VFP_SINGLE_MANTISSA_BITS)) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (s->exponent && s->exponent != 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		significand |= 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	s->significand = significand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * Re-pack a single-precision float.  This assumes that the float is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * already normalised such that the MSB is bit 30, _not_ bit 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline s32 vfp_single_pack(struct vfp_single *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	val = (s->sign << 16) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	      (s->exponent << VFP_SINGLE_MANTISSA_BITS) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	      (s->significand >> VFP_SINGLE_LOW_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return (s32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define VFP_NUMBER		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define VFP_ZERO		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define VFP_DENORMAL		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define VFP_INFINITY		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define VFP_NAN			(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define VFP_NAN_SIGNAL		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VFP_QNAN		(VFP_NAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VFP_SNAN		(VFP_NAN|VFP_NAN_SIGNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static inline int vfp_single_type(struct vfp_single *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int type = VFP_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (s->exponent == 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		if (s->significand == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			type = VFP_INFINITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		else if (s->significand & VFP_SINGLE_SIGNIFICAND_QNAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			type = VFP_QNAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			type = VFP_SNAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	} else if (s->exponent == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (s->significand == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			type |= VFP_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			type |= VFP_DENORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #ifndef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define vfp_single_normaliseround(sd,vsd,fpscr,except,func) __vfp_single_normaliseround(sd,vsd,fpscr,except)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 __vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions, const char *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * Double-precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct vfp_double {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	s16	exponent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u16	sign;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u64	significand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * VFP_REG_ZERO is a special register number for vfp_get_double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * which returns (double)0.0.  This is useful for the compare with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * zero instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #ifdef CONFIG_VFPv3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define VFP_REG_ZERO	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VFP_REG_ZERO	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) asmlinkage u64 vfp_get_double(unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) asmlinkage void vfp_put_double(u64 val, unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define VFP_DOUBLE_MANTISSA_BITS	(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define VFP_DOUBLE_EXPONENT_BITS	(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define VFP_DOUBLE_LOW_BITS		(64 - VFP_DOUBLE_MANTISSA_BITS - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define VFP_DOUBLE_LOW_BITS_MASK	((1 << VFP_DOUBLE_LOW_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * The bit in an unpacked double which indicates that it is a quiet NaN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define VFP_DOUBLE_SIGNIFICAND_QNAN	(1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * Operations on packed single-precision numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define vfp_double_packed_sign(v)	((v) & (1ULL << 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define vfp_double_packed_negate(v)	((v) ^ (1ULL << 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define vfp_double_packed_abs(v)	((v) & ~(1ULL << 63))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define vfp_double_packed_exponent(v)	(((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define vfp_double_packed_mantissa(v)	((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * Unpack a double-precision float.  Note that this returns the magnitude
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  * of the double-precision float mantissa with the 1. if necessary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * aligned to bit 62.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline void vfp_double_unpack(struct vfp_double *s, s64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u64 significand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	s->sign = vfp_double_packed_sign(val) >> 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	s->exponent = vfp_double_packed_exponent(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	significand = (u64) val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	significand = (significand << (64 - VFP_DOUBLE_MANTISSA_BITS)) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (s->exponent && s->exponent != 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		significand |= (1ULL << 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	s->significand = significand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  * Re-pack a double-precision float.  This assumes that the float is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  * already normalised such that the MSB is bit 30, _not_ bit 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static inline s64 vfp_double_pack(struct vfp_double *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	val = ((u64)s->sign << 48) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	      ((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	      (s->significand >> VFP_DOUBLE_LOW_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	return (s64)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline int vfp_double_type(struct vfp_double *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	int type = VFP_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (s->exponent == 2047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (s->significand == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			type = VFP_INFINITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		else if (s->significand & VFP_DOUBLE_SIGNIFICAND_QNAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			type = VFP_QNAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			type = VFP_SNAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	} else if (s->exponent == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		if (s->significand == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			type |= VFP_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			type |= VFP_DENORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 vfp_double_normaliseround(int dd, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)  * A special flag to tell the normalisation code not to normalise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define VFP_NAN_FLAG	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  * A bit pattern used to indicate the initial (unset) value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * exception mask, in case nothing handles an instruction.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  * doesn't include the NAN flag, which get masked out before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)  * we check for an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define VFP_EXCEPTION_ERROR	((u32)-1 & ~VFP_NAN_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * A flag to tell vfp instruction type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  *  OP_SCALAR - this operation always operates in scalar mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  *  OP_SD - the instruction exceptionally writes to a single precision result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  *  OP_DD - the instruction exceptionally writes to a double precision result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  *  OP_SM - the instruction exceptionally reads from a single precision operand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OP_SCALAR	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OP_SD		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OP_DD		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OP_SM		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) asmlinkage void vfp_save_state(void *location, u32 fpexc);