^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/probes/decode.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Some contents moved here from arch/arm/include/asm/kprobes.h which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006, 2007 Motorola Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _ARM_KERNEL_PROBES_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _ARM_KERNEL_PROBES_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/probes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/kprobes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __init arm_probes_decode_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern probes_check_cc * const probes_condition_checks[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if __LINUX_ARM_ARCH__ >= 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* str_pc_offset is architecturally defined from ARMv7 onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define str_pc_offset 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define find_str_pc_offset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #else /* __LINUX_ARM_ARCH__ < 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* We need a run-time check to determine str_pc_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) extern int str_pc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __init find_str_pc_offset(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Update ITSTATE after normal execution of an IT block instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * The 8 IT state bits are split into two parts in CPSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ITSTATE<1:0> are in CPSR<26:25>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * ITSTATE<7:2> are in CPSR<15:10>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline unsigned long it_advance(unsigned long cpsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if ((cpsr & 0x06000400) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cpsr &= ~PSR_IT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* We need to shift left ITSTATE<4:0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long it = cpsr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) it <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) it &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cpsr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) cpsr |= it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return cpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) long cpsr = regs->ARM_cpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (pcv & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cpsr |= PSR_T_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pcv &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cpsr &= ~PSR_T_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regs->ARM_cpsr = cpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regs->ARM_pc = pcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #if __LINUX_ARM_ARCH__ >= 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define load_write_pc_interworks true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define test_load_write_pc_interworking()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #else /* __LINUX_ARM_ARCH__ < 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* We need run-time testing to determine if load_write_pc() should interwork. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern bool load_write_pc_interworks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __init test_load_write_pc_interworking(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (load_write_pc_interworks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bx_write_pc(pcv, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regs->ARM_pc = pcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #if __LINUX_ARM_ARCH__ >= 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define alu_write_pc_interworks true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define test_alu_write_pc_interworking()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #elif __LINUX_ARM_ARCH__ <= 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define alu_write_pc_interworks false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define test_alu_write_pc_interworking()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #else /* __LINUX_ARM_ARCH__ == 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern bool alu_write_pc_interworks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void __init test_alu_write_pc_interworking(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* __LINUX_ARM_ARCH__ == 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (alu_write_pc_interworks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bx_write_pc(pcv, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regs->ARM_pc = pcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Test if load/store instructions writeback the address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * if P (bit 24) == 0 or W (bit 21) == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * The following definitions and macros are used to build instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * decoding tables for use by probes_decode_insn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * These tables are a concatenation of entries each of which consist of one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * the decode_* structs. All of the fields in every type of decode structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * are of the union type decode_item, therefore the entire decode table can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * viewed as an array of these and declared like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * static const union decode_item table_name[] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * In order to construct each entry in the table, macros are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * initialise a number of sequential decode_item values in a layout which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * decode_simulate by initialising four decode_item objects like this...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * {.bits = _type},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * {.bits = _mask},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * {.bits = _value},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * {.action = _handler},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Initialising a specified member of the union means that the compiler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * will produce a warning if the argument is of an incorrect type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Below is a list of each of the macros used to initialise entries and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * description of the action performed when that entry is matched to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * instruction. A match is found when (instruction & mask) == value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * DECODE_TABLE(mask, value, table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Instruction decoding jumps to parsing the new sub-table 'table'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * DECODE_CUSTOM(mask, value, decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * The value of 'decoder' is used as an index into the array of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * action functions, and the retrieved decoder function is invoked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * to complete decoding of the instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * DECODE_SIMULATE(mask, value, handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * The probes instruction handler is set to the value found by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * indexing into the action array using the value of 'handler'. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * will be used to simulate the instruction when the probe is hit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Decoding returns with INSN_GOOD_NO_SLOT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * DECODE_EMULATE(mask, value, handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * The probes instruction handler is set to the value found by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * indexing into the action array using the value of 'handler'. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * will be used to emulate the instruction when the probe is hit. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * modified instruction (see below) is placed in the probes instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * slot so it may be called by the emulation code. Decoding returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * with INSN_GOOD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * DECODE_REJECT(mask, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Instruction decoding fails with INSN_REJECTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * DECODE_OR(mask, value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * This allows the mask/value test of multiple table entries to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * logically ORed. Once an 'or' entry is matched the decoding action to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * be performed is that of the next entry which isn't an 'or'. E.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * DECODE_OR (mask1, value1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * DECODE_OR (mask2, value2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * DECODE_SIMULATE (mask3, value3, simulation_handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * This means that if any of the three mask/value pairs match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * instruction being decoded, then 'simulation_handler' will be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Both the SIMULATE and EMULATE macros have a second form which take an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * additional 'regs' argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * DECODE_SIMULATEX(mask, value, handler, regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * DECODE_EMULATEX (mask, value, handler, regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * These are used to specify what kind of CPU register is encoded in each of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * least significant 5 nibbles of the instruction being decoded. The regs value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * is specified using the REGS macro, this takes any of the REG_TYPE_* values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * from enum decode_reg_type as arguments; only the '*' part of the name is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * given. E.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * REGS(0, ANY, NOPC, 0, ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * This indicates an instruction is encoded like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * bits 19..16 ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * bits 15..12 any register allowed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * bits 11.. 8 any register except PC allowed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * bits 7.. 4 ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * bits 3.. 0 any register allowed here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * This register specification is checked after a decode table entry is found to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * match an instruction (through the mask/value test). Any invalid register then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * found in the instruction will cause decoding to fail with INSN_REJECTED. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * the above example this would happen if bits 11..8 of the instruction were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * 1111, indicating R15 or PC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * As well as checking for legal combinations of registers, this data is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * used to modify the registers encoded in the instructions so that an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Here is a real example which matches ARM instructions of the form
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * REGS(ANY, ANY, NOPC, 0, ANY)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * ^ ^ ^ ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Rn Rd Rs Rm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Rs == R15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * the kprobes instruction slot. This can then be called later by the handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * function emulate_rd12rn16rm0rs8_rwflags (a pointer to which is retrieved from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * the indicated slot in the action array), in order to simulate the instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum decode_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DECODE_TYPE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DECODE_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DECODE_TYPE_CUSTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DECODE_TYPE_SIMULATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DECODE_TYPE_EMULATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DECODE_TYPE_OR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DECODE_TYPE_REJECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) NUM_DECODE_TYPES /* Must be last enum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DECODE_TYPE_BITS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum decode_reg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) REG_TYPE_NONE = 0, /* Not a register, ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) REG_TYPE_ANY, /* Any register allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) REG_TYPE_SP, /* Register must be SP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) REG_TYPE_PC, /* Register must be PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) REG_TYPE_NOSP, /* Register must not be SP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) REG_TYPE_NOSPPC, /* Register must not be SP or PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) REG_TYPE_NOPC, /* Register must not be PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* The following types are used when the encoding for PC indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * another instruction form. This distiction only matters for test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * case coverage checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) REG_TYPE_NOPCX, /* Register must not be PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) REG_TYPE_NOSPPCX, /* Register must not be SP or PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Alias to allow '0' arg to be used in REGS macro. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) REG_TYPE_0 = REG_TYPE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define REGS(r16, r12, r8, r4, r0) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (((REG_TYPE_##r16) << 16) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ((REG_TYPE_##r12) << 12) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ((REG_TYPE_##r8) << 8) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ((REG_TYPE_##r4) << 4) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (REG_TYPE_##r0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) union decode_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const union decode_item *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct decode_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) typedef enum probes_insn (probes_custom_decode_t)(probes_opcode_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct arch_probes_insn *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct decode_header *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) union decode_action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) probes_insn_handler_t *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) probes_custom_decode_t *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) typedef enum probes_insn (probes_check_t)(probes_opcode_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct arch_probes_insn *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) const struct decode_header *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct decode_checker {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) probes_check_t *checker;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DECODE_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {.bits = DECODE_TYPE_END}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct decode_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) union decode_item type_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) union decode_item mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) union decode_item value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DECODE_HEADER(_type, _mask, _value, _regs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {.bits = (_mask)}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {.bits = (_value)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct decode_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct decode_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) union decode_item table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DECODE_TABLE(_mask, _value, _table) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {.table = (_table)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct decode_custom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct decode_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) union decode_item decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DECODE_CUSTOM(_mask, _value, _decoder) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {.action = (_decoder)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct decode_simulate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct decode_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) union decode_item handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {.action = (_handler)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define DECODE_SIMULATE(_mask, _value, _handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DECODE_SIMULATEX(_mask, _value, _handler, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct decode_emulate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct decode_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) union decode_item handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DECODE_EMULATEX(_mask, _value, _handler, _regs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {.action = (_handler)}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DECODE_EMULATE(_mask, _value, _handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DECODE_EMULATEX(_mask, _value, _handler, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct decode_or {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct decode_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DECODE_OR(_mask, _value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum probes_insn {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) INSN_REJECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) INSN_GOOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) INSN_GOOD_NO_SLOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct decode_reject {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct decode_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DECODE_REJECT(_mask, _value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) probes_insn_handler_t probes_simulate_nop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) probes_insn_handler_t probes_emulate_none;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int __kprobes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const union decode_item *table, bool thumb, bool emulate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const union decode_action *actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const struct decode_checker **checkers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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