^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * arch/arm/probes/decode-arm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Some code moved here from arch/arm/kernel/kprobes-arm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006, 2007 Motorola Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "decode.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "decode-arm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * To avoid the complications of mimicing single-stepping on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * processor without a Next-PC or a single-step mode, and to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * avoid having to deal with the side-effects of boosting, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * simulate or emulate (almost) all ARM instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * "Simulation" is where the instruction's behavior is duplicated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * C code. "Emulation" is where the original instruction is rewritten
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * and executed, often by altering its registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * By having all behavior of the kprobe'd instruction completed before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * returning from the kprobe_handler(), all locks (scheduler and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * interrupt) can safely be released. There is no need for secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * breakpoints, no race with MP or preemptable kernels, nor having to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * clean up resources counts at a later time impacting overall system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * performance. By rewriting the instruction, only the minimum registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * need to be loaded and saved back optimizing performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Calling the insnslot_*_rwflags version of a function doesn't hurt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * anything even when the CPSR flags aren't updated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * instruction. It's just a little slower in return for saving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * a little space by not having a duplicate function that doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * update the flags. (The same optimization can be said for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * instructions that do or don't perform register writeback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Also, instructions can either read the flags, only write the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * flags, or read and write the flags. To save combinations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * rather than for sheer performance, flag functions just assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * read and write of flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __kprobes simulate_bbl(probes_opcode_t insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct arch_probes_insn *asi, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) long iaddr = (long) regs->ARM_pc - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int disp = branch_displacement(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (insn & (1 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) regs->ARM_lr = iaddr + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regs->ARM_pc = iaddr + 8 + disp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __kprobes simulate_blx1(probes_opcode_t insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct arch_probes_insn *asi, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) long iaddr = (long) regs->ARM_pc - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int disp = branch_displacement(insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regs->ARM_lr = iaddr + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regs->ARM_cpsr |= PSR_T_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __kprobes simulate_blx2bx(probes_opcode_t insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct arch_probes_insn *asi, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int rm = insn & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) long rmv = regs->uregs[rm];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (insn & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regs->ARM_lr = (long) regs->ARM_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regs->ARM_pc = rmv & ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regs->ARM_cpsr &= ~PSR_T_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (rmv & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regs->ARM_cpsr |= PSR_T_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __kprobes simulate_mrs(probes_opcode_t insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct arch_probes_insn *asi, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int rd = (insn >> 12) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long mask = 0xf8ff03df; /* Mask out execution state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) regs->uregs[rd] = regs->ARM_cpsr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __kprobes simulate_mov_ipsp(probes_opcode_t insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct arch_probes_insn *asi, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regs->uregs[12] = regs->uregs[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * For the instruction masking and comparisons in all the "space_*"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * functions below, Do _not_ rearrange the order of tests unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * you're very, very sure of what you are doing. For the sake of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * efficiency, the masks for some tests sometimes assume other test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * have been done prior to them so the number of patterns to test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * for an instruction set can be as broad as possible to reduce the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * number of tests needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const union decode_item arm_1111_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Unconditional instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* memory hint 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* PLDW (immediate) 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* PLD (immediate) 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DECODE_SIMULATE (0xfe300000, 0xf4100000, PROBES_PRELOAD_IMM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* memory hint 1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* PLDI (register) 1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* PLDW (register) 1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* PLD (register) 1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DECODE_SIMULATE (0xfe300010, 0xf6100000, PROBES_PRELOAD_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* BLX (immediate) 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DECODE_SIMULATE (0xfe000000, 0xfa000000, PROBES_BRANCH_IMM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* CPS 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* SETEND 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* SRS 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* RFE 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Coprocessor instructions... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* MCRR2 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* MRRC2 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* LDC2 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* STC2 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* CDP2 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* MCR2 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* MRC2 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Other unallocated instructions... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Miscellaneous instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* MRS cpsr cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DECODE_SIMULATEX(0x0ff000f0, 0x01000000, PROBES_MRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) REGS(0, NOPC, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* BX cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DECODE_SIMULATE (0x0ff000f0, 0x01200010, PROBES_BRANCH_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* BLX (register) cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DECODE_SIMULATEX(0x0ff000f0, 0x01200030, PROBES_BRANCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) REGS(0, 0, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* CLZ cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DECODE_EMULATEX (0x0ff000f0, 0x01600010, PROBES_CLZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) REGS(0, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* QADD cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* QSUB cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* QDADD cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* QDSUB cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DECODE_EMULATEX (0x0f9000f0, 0x01000050, PROBES_SATURATING_ARITHMETIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) REGS(NOPC, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* BXJ cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* MSR cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* MRS spsr cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* BKPT 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* SMC cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* And unallocated instructions... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Halfword multiply and multiply-accumulate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* SMLALxy cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DECODE_EMULATEX (0x0ff00090, 0x01400080, PROBES_MUL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* SMULWy cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DECODE_OR (0x0ff000b0, 0x012000a0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* SMULxy cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DECODE_EMULATEX (0x0ff00090, 0x01600080, PROBES_MUL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) REGS(NOPC, 0, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* SMLAxy cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DECODE_OR (0x0ff00090, 0x01000080),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* SMLAWy cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DECODE_EMULATEX (0x0ff000b0, 0x01200080, PROBES_MUL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const union decode_item arm_cccc_0000_____1001_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Multiply and multiply-accumulate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* MUL cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* MULS cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DECODE_EMULATEX (0x0fe000f0, 0x00000090, PROBES_MUL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) REGS(NOPC, 0, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* MLA cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* MLAS cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DECODE_OR (0x0fe000f0, 0x00200090),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* MLS cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DECODE_EMULATEX (0x0ff000f0, 0x00600090, PROBES_MUL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* UMAAL cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DECODE_OR (0x0ff000f0, 0x00400090),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* UMULL cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* UMULLS cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* UMLAL cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* UMLALS cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* SMULL cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* SMULLS cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* SMLAL cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* SMLALS cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DECODE_EMULATEX (0x0f8000f0, 0x00800090, PROBES_MUL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const union decode_item arm_cccc_0001_____1001_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Synchronization primitives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #if __LINUX_ARM_ARCH__ < 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Deprecated on ARMv6 and may be UNDEFINED on v7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* SMP/SWPB cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DECODE_EMULATEX (0x0fb000f0, 0x01000090, PROBES_SWP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) REGS(NOPC, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* LDREX/STREX{,D,B,H} cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* And unallocated instructions... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const union decode_item arm_cccc_000x_____1xx1_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Extra load/store instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* STRHT cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* ??? cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* LDRHT cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* LDRSBT cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* LDRSHT cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DECODE_REJECT (0x0f200090, 0x00200090),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DECODE_REJECT (0x0e10e0d0, 0x0000e0d0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* LDRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DECODE_EMULATEX (0x0e5000d0, 0x000000d0, PROBES_LDRSTRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) REGS(NOPCWB, NOPCX, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* LDRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* STRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DECODE_EMULATEX (0x0e5000d0, 0x004000d0, PROBES_LDRSTRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) REGS(NOPCWB, NOPCX, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* STRH (register) cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DECODE_EMULATEX (0x0e5000f0, 0x000000b0, PROBES_STORE_EXTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) REGS(NOPCWB, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* LDRH (register) cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* LDRSB (register) cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* LDRSH (register) cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECODE_EMULATEX (0x0e500090, 0x00100090, PROBES_LOAD_EXTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) REGS(NOPCWB, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* STRH (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECODE_EMULATEX (0x0e5000f0, 0x004000b0, PROBES_STORE_EXTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) REGS(NOPCWB, NOPC, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* LDRH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* LDRSB (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* LDRSH (immediate) cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECODE_EMULATEX (0x0e500090, 0x00500090, PROBES_LOAD_EXTRA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) REGS(NOPCWB, NOPC, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const union decode_item arm_cccc_000x_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Data-processing (register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* <op>S PC, ... cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECODE_REJECT (0x0e10f000, 0x0010f000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* MOV IP, SP 1110 0001 1010 0000 1100 0000 0000 1101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, PROBES_MOV_IP_SP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* TST (register) cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* TEQ (register) cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* CMP (register) cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* CMN (register) cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECODE_EMULATEX (0x0f900010, 0x01100000, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) REGS(ANY, 0, 0, 0, ANY)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* MOV (register) cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* MVN (register) cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECODE_EMULATEX (0x0fa00010, 0x01a00000, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) REGS(0, ANY, 0, 0, ANY)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* AND (register) cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* EOR (register) cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* SUB (register) cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* RSB (register) cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* ADD (register) cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* ADC (register) cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* SBC (register) cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* RSC (register) cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* ORR (register) cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* BIC (register) cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECODE_EMULATEX (0x0e000010, 0x00000000, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) REGS(ANY, ANY, 0, 0, ANY)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* TST (reg-shift reg) cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* TEQ (reg-shift reg) cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) REGS(NOPC, 0, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) REGS(0, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* SUB (reg-shift reg) cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* RSB (reg-shift reg) cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* ADD (reg-shift reg) cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* ADC (reg-shift reg) cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* SBC (reg-shift reg) cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* RSC (reg-shift reg) cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const union decode_item arm_cccc_001x_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Data-processing (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* MOVW cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* MOVT cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DECODE_EMULATEX (0x0fb00000, 0x03000000, PROBES_MOV_HALFWORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) REGS(0, NOPC, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* YIELD cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DECODE_OR (0x0fff00ff, 0x03200001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* SEV cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DECODE_EMULATE (0x0fff00ff, 0x03200004, PROBES_SEV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* NOP cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* WFE cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* WFI cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DECODE_SIMULATE (0x0fff00fc, 0x03200000, PROBES_WFE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* DBG cccc 0011 0010 0000 xxxx xxxx ffff xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* unallocated hints cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* MSR (immediate) cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DECODE_REJECT (0x0fb00000, 0x03200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* <op>S PC, ... cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DECODE_REJECT (0x0e10f000, 0x0210f000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* TST (immediate) cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* TEQ (immediate) cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* CMP (immediate) cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* CMN (immediate) cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DECODE_EMULATEX (0x0f900000, 0x03100000, PROBES_DATA_PROCESSING_IMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) REGS(ANY, 0, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* MOV (immediate) cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* MVN (immediate) cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DECODE_EMULATEX (0x0fa00000, 0x03a00000, PROBES_DATA_PROCESSING_IMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) REGS(0, ANY, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* AND (immediate) cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* EOR (immediate) cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* SUB (immediate) cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* RSB (immediate) cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* ADD (immediate) cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* ADC (immediate) cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* SBC (immediate) cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* RSC (immediate) cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* ORR (immediate) cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* BIC (immediate) cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DECODE_EMULATEX (0x0e000000, 0x02000000, PROBES_DATA_PROCESSING_IMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) REGS(ANY, ANY, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const union decode_item arm_cccc_0110_____xxx1_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Media instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* SEL cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DECODE_EMULATEX (0x0ff000f0, 0x068000b0, PROBES_SATURATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) REGS(NOPC, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* SSAT cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* USAT cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DECODE_OR(0x0fa00030, 0x06a00010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* SSAT16 cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* USAT16 cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DECODE_EMULATEX (0x0fb000f0, 0x06a00030, PROBES_SATURATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) REGS(0, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* REV cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* REV16 cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* RBIT cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* REVSH cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DECODE_EMULATEX (0x0fb00070, 0x06b00030, PROBES_REV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) REGS(0, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* ??? cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DECODE_REJECT (0x0fb00010, 0x06000010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* ??? cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DECODE_REJECT (0x0f8000f0, 0x060000b0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* ??? cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DECODE_REJECT (0x0f8000f0, 0x060000d0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* SADD16 cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* SADDSUBX cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* SSUBADDX cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* SSUB16 cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* SADD8 cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* SSUB8 cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* QADD16 cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* QADDSUBX cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* QSUBADDX cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* QSUB16 cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* QADD8 cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* QSUB8 cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* SHADD16 cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* SHADDSUBX cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* SHSUBADDX cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* SHSUB16 cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* SHADD8 cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* SHSUB8 cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* UADD16 cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* UADDSUBX cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* USUBADDX cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* USUB16 cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* UADD8 cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* USUB8 cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* UQADD16 cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* UQADDSUBX cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* UQSUBADDX cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* UQSUB16 cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* UQADD8 cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* UQSUB8 cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* UHADD16 cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* UHADDSUBX cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* UHSUBADDX cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* UHSUB16 cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* UHADD8 cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* UHSUB8 cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DECODE_EMULATEX (0x0f800010, 0x06000010, PROBES_MMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) REGS(NOPC, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* PKHBT cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* PKHTB cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DECODE_EMULATEX (0x0ff00030, 0x06800010, PROBES_PACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) REGS(NOPC, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* ??? cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* ??? cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DECODE_REJECT (0x0fb000f0, 0x06900070),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* SXTB16 cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* SXTB cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* SXTH cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* UXTB16 cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* UXTB cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* UXTH cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, PROBES_EXTEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) REGS(0, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* SXTAB16 cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* SXTAB cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* SXTAH cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* UXTAB16 cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* UXTAB cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* UXTAH cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DECODE_EMULATEX (0x0f8000f0, 0x06800070, PROBES_EXTEND_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) REGS(NOPCX, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const union decode_item arm_cccc_0111_____xxx1_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Media instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* UNDEFINED cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DECODE_REJECT (0x0ff000f0, 0x07f000f0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* SMLALD cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* SMLSLD cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DECODE_EMULATEX (0x0ff00090, 0x07400010, PROBES_MUL_ADD_LONG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* SMUAD cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* SMUSD cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DECODE_OR (0x0ff0f090, 0x0700f010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* SMMUL cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) DECODE_OR (0x0ff0f0d0, 0x0750f010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* USAD8 cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, PROBES_MUL_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) REGS(NOPC, 0, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* SMLAD cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* SMLSD cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DECODE_OR (0x0ff00090, 0x07000010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* SMMLA cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DECODE_OR (0x0ff000d0, 0x07500010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* USADA8 cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) DECODE_EMULATEX (0x0ff000f0, 0x07800010, PROBES_MUL_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) REGS(NOPC, NOPCX, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* SMMLS cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) DECODE_EMULATEX (0x0ff000d0, 0x075000d0, PROBES_MUL_ADD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) REGS(NOPC, NOPC, NOPC, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* SBFX cccc 0111 101x xxxx xxxx xxxx x101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* UBFX cccc 0111 111x xxxx xxxx xxxx x101 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) DECODE_EMULATEX (0x0fa00070, 0x07a00050, PROBES_BITFIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) REGS(0, NOPC, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* BFC cccc 0111 110x xxxx xxxx xxxx x001 1111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, PROBES_BITFIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) REGS(0, NOPC, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* BFI cccc 0111 110x xxxx xxxx xxxx x001 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DECODE_EMULATEX (0x0fe00070, 0x07c00010, PROBES_BITFIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) REGS(0, NOPC, 0, 0, NOPCX)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const union decode_item arm_cccc_01xx_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Load/store word and unsigned byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* LDRB/STRB pc,[...] cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DECODE_REJECT (0x0c40f000, 0x0440f000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* STRT cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* LDRT cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* STRBT cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* LDRBT cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) DECODE_REJECT (0x0d200000, 0x04200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* STR (immediate) cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* STRB (immediate) cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DECODE_EMULATEX (0x0e100000, 0x04000000, PROBES_STORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) REGS(NOPCWB, ANY, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* LDR (immediate) cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* LDRB (immediate) cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) DECODE_EMULATEX (0x0e100000, 0x04100000, PROBES_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) REGS(NOPCWB, ANY, 0, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* STR (register) cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* STRB (register) cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) DECODE_EMULATEX (0x0e100000, 0x06000000, PROBES_STORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) REGS(NOPCWB, ANY, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* LDR (register) cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* LDRB (register) cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) DECODE_EMULATEX (0x0e100000, 0x06100000, PROBES_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) REGS(NOPCWB, ANY, 0, 0, NOPC)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const union decode_item arm_cccc_100x_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Block data transfer instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* LDM cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* STM cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DECODE_CUSTOM (0x0e400000, 0x08000000, PROBES_LDMSTM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* LDM (exception ret) cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) const union decode_item probes_decode_arm_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * Unconditional instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) DECODE_TABLE (0xf0000000, 0xf0000000, arm_1111_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Miscellaneous instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DECODE_TABLE (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Halfword multiply and multiply-accumulate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) DECODE_TABLE (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Multiply and multiply-accumulate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) DECODE_TABLE (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * Synchronization primitives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) DECODE_TABLE (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Extra load/store instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) DECODE_TABLE (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * Data-processing (register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Data-processing (register-shifted register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) DECODE_TABLE (0x0e000000, 0x00000000, arm_cccc_000x_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Data-processing (immediate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) DECODE_TABLE (0x0e000000, 0x02000000, arm_cccc_001x_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * Media instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) DECODE_TABLE (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) DECODE_TABLE (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * Load/store word and unsigned byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) DECODE_TABLE (0x0c000000, 0x04000000, arm_cccc_01xx_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Block data transfer instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DECODE_TABLE (0x0e000000, 0x08000000, arm_cccc_100x_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* B cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* BL cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) DECODE_SIMULATE (0x0e000000, 0x0a000000, PROBES_BRANCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Supervisor Call, and coprocessor instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* MCRR cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* MRRC cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* LDC cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* STC cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* CDP cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* MCR cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* MRC cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* SVC cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) DECODE_REJECT (0x0c000000, 0x0c000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) DECODE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #ifdef CONFIG_ARM_KPROBES_TEST_MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) EXPORT_SYMBOL_GPL(probes_decode_arm_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void __kprobes arm_singlestep(probes_opcode_t insn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct arch_probes_insn *asi, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) regs->ARM_pc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) asi->insn_handler(insn, asi, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * INSN_REJECTED If instruction is one not allowed to kprobe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * INSN_GOOD If instruction is supported and uses instruction slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * For instructions we don't want to kprobe (INSN_REJECTED return result):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * These are generally ones that modify the processor state making
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * them "hard" to simulate such as switches processor modes or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * make accesses in alternate modes. Any of these could be simulated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * if the work was put into it, but low return considering they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * should also be very rare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) enum probes_insn __kprobes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) arm_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) bool emulate, const union decode_action *actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) const struct decode_checker *checkers[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) asi->insn_singlestep = arm_singlestep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) asi->insn_check_cc = probes_condition_checks[insn>>28];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return probes_decode_insn(insn, asi, probes_decode_arm_table, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) emulate, actions, checkers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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