^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/plat-orion/time.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell Orion SoC timer handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Timer 0 is used as free-running clocksource, while timer 1 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * used as clock_event_device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <plat/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * MBus bridge block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BRIDGE_CAUSE_OFF 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BRIDGE_MASK_OFF 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BRIDGE_INT_TIMER0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BRIDGE_INT_TIMER1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Timer block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIMER_CTRL_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TIMER0_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIMER0_RELOAD_EN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TIMER1_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TIMER1_RELOAD_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TIMER0_RELOAD_OFF 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TIMER0_VAL_OFF 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TIMER1_RELOAD_OFF 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TIMER1_VAL_OFF 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * SoC-specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void __iomem *bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u32 bridge_timer1_clr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __iomem *timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Number of timer ticks per jiffy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static u32 ticks_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Orion's sched_clock implementation. It has a resolution of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * at least 7.5ns (133MHz TCLK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static u64 notrace orion_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ~readl(timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Clockevent handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (delta == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Clear and enable clockevent timer interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u = readl(bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u |= BRIDGE_INT_TIMER1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(u, bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Setup new clockevent timer value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(delta, timer_base + TIMER1_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Enable the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u = readl(timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel(u, timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int orion_clkevt_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Disable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u = readl(timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Disable timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u = readl(bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* ACK pending timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int orion_clkevt_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Setup timer to fire at 1/HZ intervals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Enable timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u = readl(bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Enable timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u = readl(timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct clock_event_device orion_clkevt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "orion_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .features = CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .set_next_event = orion_clkevt_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .set_state_shutdown = orion_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .set_state_periodic = orion_clkevt_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .set_state_oneshot = orion_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .tick_resume = orion_clkevt_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * ACK timer interrupt and call event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) orion_clkevt.event_handler(&orion_clkevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) orion_time_set_base(void __iomem *_timer_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) timer_base = _timer_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static unsigned long orion_delay_timer_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ~readl(timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct delay_timer orion_delay_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .read_current_timer = orion_delay_timer_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int irq, unsigned int tclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Set SoC-specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bridge_base = _bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ticks_per_jiffy = (tclk + HZ/2) / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) orion_delay_timer.freq = tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) register_current_timer_delay(&orion_delay_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Set scale and timer for sched_clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sched_clock_register(orion_read_sched_clock, 32, tclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Setup free-running clocksource timer (interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * disabled).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u = readl(bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u = readl(timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) tclk, 300, 32, clocksource_mmio_readl_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Setup clockevent timer (interrupt-driven).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (request_irq(irq, orion_timer_interrupt, IRQF_TIMER, "orion_tick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pr_err("Failed to request irq %u (orion_tick)\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) orion_clkevt.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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