^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/plat-orion/pcie.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Marvell Orion SoC PCIe handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <plat/pcie.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <plat/addr-map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * PCIe unit register offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIE_DEV_ID_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCIE_CMD_OFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCIE_DEV_REV_OFF 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCIE_HEADER_LOG_4_OFF 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIE_WIN5_CTRL_OFF 0x1880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_WIN5_BASE_OFF 0x1884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_WIN5_REMAP_OFF 0x188c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_CONF_ADDR_OFF 0x18f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_CONF_ADDR_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIE_CONF_DATA_OFF 0x18fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCIE_MASK_OFF 0x1910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCIE_CTRL_OFF 0x1a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCIE_CTRL_X1_MODE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCIE_STAT_OFF 0x1a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCIE_STAT_DEV_OFFS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCIE_STAT_DEV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCIE_STAT_BUS_OFFS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCIE_STAT_BUS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCIE_STAT_LINK_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCIE_DEBUG_CTRL 0x1a60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCIE_DEBUG_SOFT_RESET (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 orion_pcie_dev_id(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return readl(base + PCIE_DEV_ID_OFF) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 orion_pcie_rev(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return readl(base + PCIE_DEV_REV_OFF) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int orion_pcie_link_up(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int __init orion_pcie_x4_mode(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int orion_pcie_get_local_bus_nr(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 stat = readl(base + PCIE_STAT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) stat = readl(base + PCIE_STAT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) stat |= nr << PCIE_STAT_BUS_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(stat, base + PCIE_STAT_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __init orion_pcie_reset(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * MV-S104860-U0, Rev. C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * PCI Express Unit Soft Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * When set, generates an internal reset in the PCI Express unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * This bit should be cleared after the link is re-established.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg = readl(base + PCIE_DEBUG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg |= PCIE_DEBUG_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(reg, base + PCIE_DEBUG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (orion_pcie_link_up(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg &= ~(PCIE_DEBUG_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(reg, base + PCIE_DEBUG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Setup PCIE BARs and Address Decode Wins:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * WIN[0-3] -> DRAM bank[0-3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void __init orion_pcie_setup_wins(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct mbus_dram_target_info *dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dram = mv_mbus_dram_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * First, disable and clear BARs and windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 1; i <= 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(0, base + PCIE_BAR_CTRL_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(0, base + PCIE_BAR_LO_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(0, base + PCIE_BAR_HI_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(0, base + PCIE_WIN04_CTRL_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(0, base + PCIE_WIN04_BASE_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(0, base + PCIE_WIN04_REMAP_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(0, base + PCIE_WIN5_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(0, base + PCIE_WIN5_BASE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(0, base + PCIE_WIN5_REMAP_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Setup windows for DDR banks. Count total DDR size on the fly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) for (i = 0; i < dram->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct mbus_dram_window *cs = dram->cs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(0, base + PCIE_WIN04_REMAP_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(((cs->size - 1) & 0xffff0000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (cs->mbus_attr << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (dram->mbus_dram_target_id << 4) | 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) base + PCIE_WIN04_CTRL_OFF(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) size += cs->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Round up 'size' to the nearest power of two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if ((size & (size - 1)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) size = 1 << fls(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Setup BAR[1] to all DRAM banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(0, base + PCIE_BAR_HI_OFF(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __init orion_pcie_setup(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Point PCIe unit MBUS decode windows to DRAM space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) orion_pcie_setup_wins(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Master + slave enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cmd = readw(base + PCIE_CMD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cmd |= PCI_COMMAND_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cmd |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cmd |= PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writew(cmd, base + PCIE_CMD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Enable interrupt lines A-D.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask = readl(base + PCIE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mask |= 0x0f000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writel(mask, base + PCIE_MASK_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 devfn, int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(PCIE_CONF_BUS(bus->number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PCIE_CONF_DEV(PCI_SLOT(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) base + PCIE_CONF_ADDR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *val = readl(base + PCIE_CONF_DATA_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *val = (*val >> (8 * (where & 3))) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *val = (*val >> (8 * (where & 3))) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 devfn, int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writel(PCIE_CONF_BUS(bus->number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PCIE_CONF_DEV(PCI_SLOT(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) base + PCIE_CONF_ADDR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *val = readl(base + PCIE_CONF_DATA_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (bus->number != orion_pcie_get_local_bus_nr(base) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PCI_FUNC(devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *val = readl(base + PCIE_HEADER_LOG_4_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *val = (*val >> (8 * (where & 3))) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *val = (*val >> (8 * (where & 3))) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 devfn, int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PCIE_CONF_DEV(PCI_SLOT(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PCIE_CONF_REG(where)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *val = (*val >> (8 * (where & 3))) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *val = (*val >> (8 * (where & 3))) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 devfn, int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int ret = PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(PCIE_CONF_BUS(bus->number) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PCIE_CONF_DEV(PCI_SLOT(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) base + PCIE_CONF_ADDR_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (size == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(val, base + PCIE_CONF_DATA_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } else if (size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } else if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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