^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) NetWinder Floating Point Emulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) (c) Rebel.COM, 1998,1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) (c) Philip Blundell, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __FPOPCODE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __FPOPCODE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ARM Floating Point Instruction Classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CPDT data transfer instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) LDF, STF, LFM (copro 2), SFM (copro 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CPDO dyadic arithmetic instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ADF, MUF, SUF, RSF, DVF, RDF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) POW, RPW, RMF, FML, FDV, FRD, POL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CPDO monadic arithmetic instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) CPRT joint arithmetic/data transfer instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FIX (arithmetic followed by load/store)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FLT (load/store followed by arithmetic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CMF, CNF CMFE, CNFE (comparisons)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) WFS, RFS (write/read floating point status register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) WFC, RFC (write/read floating point control register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cond condition codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) P pre/post index bit: 0 = postindex, 1 = preindex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) U up/down bit: 0 = stack grows down, 1 = stack grows up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) W write back bit: 1 = update base register (Rn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) L load/store bit: 0 = store, 1 = load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Rn base register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Rd destination/source register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Fd floating point destination register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Fn floating point source register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Fm floating point source register or floating point constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uv transfer length (TABLE 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) wx register count (TABLE 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) abcd arithmetic opcode (TABLES 3 & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ef destination size (rounding precision) (TABLE 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) gh rounding mode (TABLE 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) j dyadic/monadic bit: 0 = dyadic, 1 = monadic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) i constant bit: 1 = constant (TABLE 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) TABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) +-------------------------+---+---+---------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) | Precision | u | v | FPSR.EP | length |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) +-------------------------+---+---+---------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) | Single | 0 | 0 | x | 1 words |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) | Double | 1 | 1 | x | 2 words |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) | Extended | 1 | 1 | x | 3 words |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) | Packed decimal | 1 | 1 | 0 | 3 words |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) | Expanded packed decimal | 1 | 1 | 1 | 4 words |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) +-------------------------+---+---+---------+---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Note: x = don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) TABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) +---+---+---------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) | w | x | Number of registers to transfer |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) +---+---+---------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) | 0 | 1 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) | 1 | 0 | 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) | 1 | 1 | 3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) | 0 | 0 | 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) +---+---+---------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) TABLE 3: Dyadic Floating Point Opcodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) +---+---+---+---+----------+-----------------------+-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) | a | b | c | d | Mnemonic | Description | Operation |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) +---+---+---+---+----------+-----------------------+-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) | 1 | 1 | 0 | 1 | | undefined instruction | trap |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) | 1 | 1 | 1 | 0 | | undefined instruction | trap |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | 1 | 1 | 1 | 1 | | undefined instruction | trap |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) +---+---+---+---+----------+-----------------------+-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Note: POW, RPW, POL are deprecated, and are available for backwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) compatibility only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) TABLE 4: Monadic Floating Point Opcodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) +---+---+---+---+----------+-----------------------+-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) | a | b | c | d | Mnemonic | Description | Operation |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) +---+---+---+---+----------+-----------------------+-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) +---+---+---+---+----------+-----------------------+-----------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) available for backwards compatibility only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) TABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) +-------------------------+---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) | Rounding Precision | e | f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) +-------------------------+---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) | IEEE Single precision | 0 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) | IEEE Double precision | 0 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) | IEEE Extended precision | 1 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) | undefined (trap) | 1 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) +-------------------------+---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) +---------------------------------+---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) | Rounding Mode | g | h |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) +---------------------------------+---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) | Round to nearest (default) | 0 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) | Round toward plus infinity | 0 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) | Round toward negative infinity | 1 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) | Round toward zero | 1 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) +---------------------------------+---+---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) === Definitions for load and store instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BIT_PREINDEX 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BIT_UP 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BIT_WRITE_BACK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BIT_LOAD 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* masks for load/store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MASK_CPDT 0x0c000000 /* data processing opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MASK_OFFSET 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MASK_TRANSFER_LENGTH 0x00408000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MASK_COPROCESSOR 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Tests for transfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TRANSFER_SINGLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TRANSFER_DOUBLE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TRANSFER_EXTENDED 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TRANSFER_PACKED MASK_TRANSFER_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Get the coprocessor number from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Get the offset from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define getOffset(opcode) (opcode & MASK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Tests for specific data transfer load/store opcodes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LOAD(opcode) ((opcode & BIT_LOAD) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define STORE(opcode) ((opcode & BIT_LOAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) === Definitions for arithmetic instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define BIT_MONADIC 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define BIT_CONSTANT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* instruction identification masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MASK_CPDO 0x0e000000 /* arithmetic opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MASK_ARITHMETIC_OPCODE 0x00f08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MASK_DESTINATION_SIZE 0x00080080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* dyadic arithmetic opcodes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ADF_CODE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MUF_CODE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SUF_CODE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define RSF_CODE 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DVF_CODE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define RDF_CODE 0x00500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define POW_CODE 0x00600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define RPW_CODE 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define RMF_CODE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FML_CODE 0x00900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FDV_CODE 0x00a00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FRD_CODE 0x00b00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define POL_CODE 0x00c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* 0x00d00000 is an invalid dyadic arithmetic opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* 0x00e00000 is an invalid dyadic arithmetic opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* 0x00f00000 is an invalid dyadic arithmetic opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* monadic arithmetic opcodes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MVF_CODE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MNF_CODE 0x00108000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ABS_CODE 0x00208000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RND_CODE 0x00308000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SQT_CODE 0x00408000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define LOG_CODE 0x00508000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LGN_CODE 0x00608000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EXP_CODE 0x00708000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SIN_CODE 0x00808000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define COS_CODE 0x00908000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TAN_CODE 0x00a08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ASN_CODE 0x00b08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ACS_CODE 0x00c08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ATN_CODE 0x00d08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define URD_CODE 0x00e08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define NRM_CODE 0x00f08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) === Definitions for register transfer and comparison instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MASK_CPRT 0x0e000010 /* register transfer opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MASK_CPRT_CODE 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define FLT_CODE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define FIX_CODE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define WFS_CODE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RFS_CODE 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define WFC_CODE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RFC_CODE 0x00500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CMF_CODE 0x00900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CNF_CODE 0x00b00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CMFE_CODE 0x00d00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CNFE_CODE 0x00f00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) === Common definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MASK_Rd 0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MASK_Rn 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MASK_Fd 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MASK_Fm 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MASK_Fn 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* condition code masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CC_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CC_NEGATIVE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CC_ZERO 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CC_CARRY 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CC_OVERFLOW 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CC_EQ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CC_NE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CC_CS 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CC_HS CC_CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CC_CC 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CC_LO CC_CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CC_MI 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CC_PL 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CC_VS 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CC_VC 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CC_HI 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CC_LS 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CC_GE 0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CC_LT 0xb0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CC_GT 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CC_LE 0xd0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CC_AL 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CC_NV 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* rounding masks/values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MASK_ROUNDING_MODE 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ROUND_TO_NEAREST 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ROUND_TO_PLUS_INFINITY 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ROUND_TO_MINUS_INFINITY 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ROUND_TO_ZERO 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MASK_ROUNDING_PRECISION 0x00080080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ROUND_SINGLE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ROUND_DOUBLE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ROUND_EXTENDED 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Get the condition code from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define getCondition(opcode) (opcode >> 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Get the source register from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define getRn(opcode) ((opcode & MASK_Rn) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Get the destination floating point register from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define getFd(opcode) ((opcode & MASK_Fd) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Get the first source floating point register from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define getFn(opcode) ((opcode & MASK_Fn) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Get the second source floating point register from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define getFm(opcode) (opcode & MASK_Fm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Get the destination register from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define getRd(opcode) ((opcode & MASK_Rd) >> 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Get the rounding mode from the opcode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_FPE_NWFPE_XP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline floatx80 __pure getExtendedConstant(const unsigned int nIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) extern const floatx80 floatx80Constant[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return floatx80Constant[nIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static inline float64 __pure getDoubleConstant(const unsigned int nIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) extern const float64 float64Constant[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return float64Constant[nIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline float32 __pure getSingleConstant(const unsigned int nIndex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) extern const float32 float32Constant[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return float32Constant[nIndex];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static inline unsigned int getTransferLength(const unsigned int opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int nRc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (opcode & MASK_TRANSFER_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case 0x00000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) nRc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break; /* single precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 0x00008000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) nRc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break; /* double precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case 0x00400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) nRc = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break; /* extended precision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) nRc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return (nRc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static inline unsigned int getRegisterCount(const unsigned int opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int nRc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) switch (opcode & MASK_REGISTER_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case 0x00000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) nRc = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case 0x00008000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) nRc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case 0x00400000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) nRc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case 0x00408000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) nRc = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) nRc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return (nRc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline unsigned int getRoundingPrecision(const unsigned int opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int nRc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch (opcode & MASK_ROUNDING_PRECISION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 0x00000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) nRc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 0x00000080:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) nRc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case 0x00080000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) nRc = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) nRc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return (nRc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline unsigned int getDestinationSize(const unsigned int opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int nRc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) switch (opcode & MASK_DESTINATION_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 0x00000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) nRc = typeSingle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case 0x00000080:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) nRc = typeDouble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 0x00080000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) nRc = typeExtended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) nRc = typeNone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return (nRc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) extern const float64 float64Constant[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) extern const float32 float32Constant[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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