Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)     NetWinder Floating Point Emulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)     (c) Rebel.COM, 1998,1999
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)     Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)     This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)     it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)     the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)     This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)     but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)     GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline unsigned long readRegister(const unsigned int nReg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	/* Note: The CPU thinks it has dealt with the current instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	   As a result the program counter has been advanced to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	   instruction, and points 4 bytes beyond the actual instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	   that caused the invalid instruction trap to occur.  We adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	   for this in this routine.  LDF/STF instructions with Rn = PC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	   depend on the PC being correct, as they use PC+8 in their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	   address calculations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct pt_regs *regs = GET_USERREG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned int val = regs->uregs[nReg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (REG_PC == nReg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		val -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writeRegister(const unsigned int nReg, const unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct pt_regs *regs = GET_USERREG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	regs->uregs[nReg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline unsigned long readCPSR(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	return (readRegister(REG_CPSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline void writeCPSR(const unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	writeRegister(REG_CPSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline unsigned long readConditionCodes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef __FPEM_TEST__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	return (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	return (readCPSR() & CC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void writeConditionCodes(const unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	struct pt_regs *regs = GET_USERREG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	unsigned long rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	 * Operate directly on userRegisters since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	 * the CPSR may be the PC register itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	rval = regs->ARM_cpsr & ~CC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	regs->ARM_cpsr = rval | (val & CC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }