Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/mm/tlb-v7.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 1997-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Modified for ARMv7 by Catalin Marinas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *  ARM architecture version 6 TLB handling functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *  These assume a split I/D TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *	v7wbi_flush_user_tlb_range(start, end, vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *	Invalidate a range of TLB entries in the specified address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  *	- start - start address (may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *	- end   - end address (exclusive, may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *	- vma   - vma_struct describing address range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *	It is assumed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  *	- the "Invalidate single entry" instruction will invalidate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *	  both the I and the D TLBs on Harvard-style TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ENTRY(v7wbi_flush_user_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	vma_vm_mm r3, r2			@ get vma->vm_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	mmid	r3, r3				@ get vm_mm->context.id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	dsb	ish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	mov	r1, r1, lsr #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	asid	r3, r3				@ mask ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_ARM_ERRATA_720789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	ALT_SMP(W(mov)	r3, #0	)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	ALT_UP(W(nop)		)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	mov	r1, r1, lsl #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_ARM_ERRATA_720789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	ALT_SMP(mcr	p15, 0, r0, c8, c3, 3)	@ TLB invalidate U MVA all ASID (shareable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	dsb	ish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ENDPROC(v7wbi_flush_user_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  *	v7wbi_flush_kern_tlb_range(start,end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  *	Invalidate a range of kernel TLB entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  *	- start - start address (may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  *	- end   - end address (exclusive, may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ENTRY(v7wbi_flush_kern_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	dsb	ish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	mov	r1, r1, lsr #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	mov	r0, r0, lsl #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	mov	r1, r1, lsl #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_ARM_ERRATA_720789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	ALT_SMP(mcr	p15, 0, r0, c8, c3, 3)	@ TLB invalidate U MVA all ASID (shareable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	ALT_SMP(mcr	p15, 0, r0, c8, c3, 1)	@ TLB invalidate U MVA (shareable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	ALT_UP(mcr	p15, 0, r0, c8, c7, 1)	@ TLB invalidate U MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	dsb	ish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ENDPROC(v7wbi_flush_kern_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	__INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 	define_tlb_functions v7wbi, v7wbi_tlb_flags_up, flags_smp=v7wbi_tlb_flags_smp