Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/mm/tlb-v6.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 1997-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  ARM architecture version 6 TLB handling functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *  These assume a split I/D TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HARVARD_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *	v6wbi_flush_user_tlb_range(start, end, vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *	Invalidate a range of TLB entries in the specified address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *	- start - start address (may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *	- end   - end address (exclusive, may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *	- vma   - vma_struct describing address range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  *	It is assumed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *	- the "Invalidate single entry" instruction will invalidate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *	  both the I and the D TLBs on Harvard-style TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ENTRY(v6wbi_flush_user_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	vma_vm_mm r3, r2			@ get vma->vm_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	mmid	r3, r3				@ get vm_mm->context.id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	mcr	p15, 0, ip, c7, c10, 4		@ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	mov	r1, r1, lsr #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	asid	r3, r3				@ mask ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	mov	r1, r1, lsl #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	vma_vm_flags r2, r2			@ get vma->vm_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef HARVARD_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	mcr	p15, 0, r0, c8, c6, 1		@ TLB invalidate D MVA (was 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	tst	r2, #VM_EXEC			@ Executable area ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	mcrne	p15, 0, r0, c8, c5, 1		@ TLB invalidate I MVA (was 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate MVA (was 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	mcr	p15, 0, ip, c7, c10, 4		@ data synchronization barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  *	v6wbi_flush_kern_tlb_range(start,end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  *	Invalidate a range of kernel TLB entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  *	- start - start address (may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  *	- end   - end address (exclusive, may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ENTRY(v6wbi_flush_kern_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	mov	r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	mov	r1, r1, lsr #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	mov	r0, r0, lsl #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	mov	r1, r1, lsl #PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef HARVARD_TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	mcr	p15, 0, r0, c8, c6, 1		@ TLB invalidate D MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	mcr	p15, 0, r0, c8, c5, 1		@ TLB invalidate I MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate MVA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	mcr	p15, 0, r2, c7, c10, 4		@ data synchronization barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	mcr	p15, 0, r2, c7, c5, 4		@ prefetch flush (isb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	__INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	define_tlb_functions v6wbi, v6wbi_tlb_flags