Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/mm/tlbv4wb.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 1997-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  ARM architecture version 4 TLB handling functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *  These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *  Processors: SA110 SA1100 SA1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *	v4wb_flush_user_tlb_range(start, end, mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *	Invalidate a range of TLB entries in the specified address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *	- start - range start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *	- end   - range end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *	- mm    - mm_struct describing address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ENTRY(v4wb_flush_user_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	vma_vm_mm ip, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	act_mm	r3				@ get current->active_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	eors	r3, ip, r3				@ == mm ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	retne	lr				@ no, we dont do anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	vma_vm_flags r2, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	mcrne	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	bic	r0, r0, #0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	bic	r0, r0, #0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  *	v4_flush_kern_tlb_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  *	Invalidate a range of TLB entries in the specified kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  *	address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  *	- start - virtual address (may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  *	- end   - virtual address (may not be aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ENTRY(v4wb_flush_kern_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	mov	r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	bic	r0, r0, #0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	bic	r0, r0, #0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	mcr	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	define_tlb_functions v4wb, v4wb_tlb_flags