Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  linux/arch/arm/mm/tlb-fa.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2005 Faraday Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Based on tlb-v4wbi.S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *  Copyright (C) 1997-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *  ARM architecture version 4, Faraday variation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *  This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *  Processors: FA520 FA526 FA626
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *	flush_user_tlb_range(start, end, mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *	Invalidate a range of TLB entries in the specified address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  *	- start - range start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *	- end   - range end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *	- mm    - mm_struct describing address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ENTRY(fa_flush_user_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	vma_vm_mm ip, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	act_mm	r3				@ get current->active_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	eors	r3, ip, r3			@ == mm ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	retne	lr				@ no, we dont do anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	mov	r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	bic	r0, r0, #0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	bic	r0, r0, #0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 1:	mcr	p15, 0, r0, c8, c7, 1		@ invalidate UTLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	mcr	p15, 0, r3, c7, c10, 4		@ data write barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ENTRY(fa_flush_kern_tlb_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	mov	r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	bic	r0, r0, #0x0ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	bic	r0, r0, #0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 1:	mcr	p15, 0, r0, c8, c7, 1		@ invalidate UTLB entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	add	r0, r0, #PAGE_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	mcr	p15, 0, r3, c7, c10, 4		@ data write barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	mcr	p15, 0, r3, c7, c5, 4		@ prefetch flush (isb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	define_tlb_functions fa, fa_tlb_flags