Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Copyright (C) 2015 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This assembly is required to safely remap the physical address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * for Keystone 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	.section ".idmap.text", "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define L1_ORDER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L2_ORDER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ENTRY(lpae_pgtables_remap_asm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	stmfd	sp!, {r4-r8, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	mrc	p15, 0, r8, c1, c0, 0		@ read control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	bic	ip, r8, #CR_M			@ disable caches and MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	mcr	p15, 0, ip, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	/* Update level 2 entries covering the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	ldr	r6, =(_end - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	add	r7, r2, #0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	add	r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	add	r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 1:	ldrd	r4, r5, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	adds	r4, r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	adc	r5, r5, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	strd	r4, r5, [r7], #1 << L2_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	cmp	r7, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	bls	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	/* Update level 2 entries for the boot data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	add	r7, r2, #0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	movw	r3, #FDT_FIXED_BASE >> (SECTION_SHIFT - L2_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	add	r7, r7, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	ldrd	r4, r5, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	adds	r4, r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	adc	r5, r5, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	strd	r4, r5, [r7], #1 << L2_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	ldrd	r4, r5, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	adds	r4, r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	adc	r5, r5, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	strd	r4, r5, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* Update level 1 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	mov	r6, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	mov	r7, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 2:	ldrd	r4, r5, [r7]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	adds	r4, r4, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	adc	r5, r5, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	strd	r4, r5, [r7], #1 << L1_ORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	subs	r6, r6, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	bne	2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	mrrc	p15, 0, r4, r5, c2		@ read TTBR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	adds	r4, r4, r0			@ update physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	adc	r5, r5, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	mcrr	p15, 0, r4, r5, c2		@ write back TTBR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	mrrc	p15, 1, r4, r5, c2		@ read TTBR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	adds	r4, r4, r0			@ update physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	adc	r5, r5, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	mcrr	p15, 1, r4, r5, c2		@ write back TTBR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	mcr	p15, 0, ip, c7, c5, 0		@ I+BTB cache invalidate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	mcr	p15, 0, ip, c8, c7, 0		@ local_flush_tlb_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	mcr	p15, 0, r8, c1, c0, 0		@ re-enable MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	ldmfd	sp!, {r4-r8, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ENDPROC(lpae_pgtables_remap_asm)