Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-v7m.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2008 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  This is the "shell" of the ARMv7-M processor support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/v7m.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) ENTRY(cpu_v7m_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) ENDPROC(cpu_v7m_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) ENTRY(cpu_v7m_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) ENDPROC(cpu_v7m_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *	cpu_v7m_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	Perform a soft reset of the system.  Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *	same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *	to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *	- loc   - location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) ENTRY(cpu_v7m_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) ENDPROC(cpu_v7m_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *	cpu_v7m_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *	Idle the processor (eg, wait for interrupt).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *	IRQs are already disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) ENTRY(cpu_v7m_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) ENDPROC(cpu_v7m_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) ENTRY(cpu_v7m_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) ENDPROC(cpu_v7m_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * There is no MMU, so here is nothing to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) ENTRY(cpu_v7m_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) ENDPROC(cpu_v7m_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) .globl	cpu_v7m_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) .equ	cpu_v7m_suspend_size, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) ENTRY(cpu_v7m_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) ENDPROC(cpu_v7m_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) ENTRY(cpu_v7m_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) ENDPROC(cpu_v7m_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) ENTRY(cpu_cm7_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	dcache_line_size r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	movw	r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	movt	r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 1:	str	r0, [r3]		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	add	r0, r0, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	subs	r1, r1, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) ENDPROC(cpu_cm7_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) ENTRY(cpu_cm7_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	movw	r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	movt	r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ldr	r0, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	bic	r0, r0, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	str	r0, [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) ENDPROC(cpu_cm7_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.section ".init.text", "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) __v7m_cm7_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mov	r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	b	__v7m_setup_cont
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *	__v7m_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  *	This should be able to cover all ARMv7-M cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __v7m_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	mov	r8, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __v7m_setup_cont:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	@ Configure the vector table base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ldr	r0, =BASEADDR_V7M_SCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	ldr	r12, =vector_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	str	r12, [r0, V7M_SCB_VTOR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	@ enable UsageFault, BusFault and MemManage fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ldr	r5, [r0, #V7M_SCB_SHCSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	orr	r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	str	r5, [r0, #V7M_SCB_SHCSR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	@ Lower the priority of the SVC and PendSV exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	mov	r5, #0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	str	r5, [r0, V7M_SCB_SHPR2]	@ set SVC priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	mov	r5, #0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	str	r5, [r0, V7M_SCB_SHPR3]	@ set PendSV priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	@ SVC to switch to handler mode. Notice that this requires sp to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	@ point to writeable memory because the processor saves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	@ some registers to the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	badr	r1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ldr	r5, [r12, #11 * 4]	@ read the SVC vector entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	str	r1, [r12, #11 * 4]	@ write the temporary SVC vector entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mov	r6, lr			@ save LR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ldr	sp, =init_thread_union + THREAD_START_SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	cpsie	i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	svc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 1:	cpsid	i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* Calculate exc_ret */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	orr	r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ldmia	sp, {r0-r3, r12}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mov	lr, r6			@ restore LR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	@ Special-purpose control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mov	r1, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	msr	control, r1		@ Thread mode has unpriviledged access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	@ Configure caches (if implemented)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	teq     r8, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	stmiane	sp, {r0-r6, lr}		@ v7m_invalidate_l1 touches r0-r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	blne	v7m_invalidate_l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	teq     r8, #0			@ re-evalutae condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ldmiane	sp, {r0-r6, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	@ Configure the System Control Register to ensure 8-byte stack alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	@ Note the STKALIGN bit is either RW or RAO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ldr	r0, [r0, V7M_SCB_CCR]   @ system control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	orr	r0, #V7M_SCB_CCR_STKALIGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	orr	r0, r0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ENDPROC(__v7m_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * Cortex-M7 processor functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	globl_equ	cpu_cm7_proc_init,	cpu_v7m_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	globl_equ	cpu_cm7_reset,		cpu_v7m_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	globl_equ	cpu_cm7_do_idle,	cpu_v7m_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	globl_equ	cpu_cm7_switch_mm,	cpu_v7m_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	string cpu_arch_name, "armv7m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	string cpu_elf_name "v7m"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	string cpu_v7m_name "ARMv7-M"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0,  proc_fns = v7m_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.long	0			/* proc_info_list.__cpu_mm_mmu_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.long	0			/* proc_info_list.__cpu_io_mmu_flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	initfn	\initfunc, \name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.long	HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \hwcaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.long	cpu_v7m_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.long   \proc_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.long	0			/* proc_info_list.tlb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.long	0			/* proc_info_list.user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.long	\cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * Match ARM Cortex-M7 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.type	__v7m_cm7_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __v7m_cm7_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.long	0x410fc270		/* ARM Cortex-M7 0xC27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.long	0xff0ffff0		/* Mask off revision, patch release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.size	__v7m_cm7_proc_info, . - __v7m_cm7_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 * Match ARM Cortex-M4 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.type	__v7m_cm4_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __v7m_cm4_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.long	0x410fc240		/* ARM Cortex-M4 0xC24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.long	0xff0ffff0		/* Mask off revision, patch release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.size	__v7m_cm4_proc_info, . - __v7m_cm4_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * Match ARM Cortex-M3 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.type	__v7m_cm3_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __v7m_cm3_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.long	0x410fc230		/* ARM Cortex-M3 0xC23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.long	0xff0ffff0		/* Mask off revision, patch release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	__v7m_proc __v7m_cm3_proc_info, __v7m_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.size	__v7m_cm3_proc_info, . - __v7m_cm3_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * Match any ARMv7-M processor core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.type	__v7m_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __v7m_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.long	0x000f0000		@ Required ID value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.long	0x000f0000		@ Mask for ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	__v7m_proc __v7m_proc_info, __v7m_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.size	__v7m_proc_info, . - __v7m_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)