^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/proc-v7.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This is the "shell" of the ARMv7 processor support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "proc-v7-3level.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "proc-v7-2level.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ENTRY(cpu_v7_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ENDPROC(cpu_v7_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ENTRY(cpu_v7_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) mrc p15, 0, r0, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) bic r0, r0, #0x1000 @ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bic r0, r0, #0x0006 @ .............ca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ENDPROC(cpu_v7_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * cpu_v7_reset(loc, hyp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Perform a soft reset of the system. Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * - loc - location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - hyp - indicate if restart occurs in HYP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * This code must be executed using a flat identity mapping with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * caches disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ENTRY(cpu_v7_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mrc p15, 0, r2, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bic r2, r2, #0x1 @ ...............m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mcr p15, 0, r2, c1, c0, 0 @ disable MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_ARM_VIRT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) teq r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bne __hyp_soft_restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bx r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ENDPROC(cpu_v7_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * cpu_v7_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Idle the processor (eg, wait for interrupt).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * IRQs are already disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ENTRY(cpu_v7_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dsb @ WFI may enter a low-power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ENDPROC(cpu_v7_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ENTRY(cpu_v7_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ALT_UP_B(1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 1: dcache_line_size r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) add r0, r0, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) subs r1, r1, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bhi 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dsb ishst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ENDPROC(cpu_v7_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_ARM_PSCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .arch_extension sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ENTRY(cpu_v7_smc_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) stmfd sp!, {r0 - r3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) smc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ldmfd sp!, {r0 - r3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) b cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ENDPROC(cpu_v7_smc_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .arch_extension virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ENTRY(cpu_v7_hvc_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) stmfd sp!, {r0 - r3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hvc #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ldmfd sp!, {r0 - r3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) b cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ENDPROC(cpu_v7_hvc_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ENTRY(cpu_v7_iciallu_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mcr p15, 0, r3, c7, c5, 0 @ ICIALLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) b cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ENDPROC(cpu_v7_iciallu_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ENTRY(cpu_v7_bpiall_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) b cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ENDPROC(cpu_v7_bpiall_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) string cpu_v7_name, "ARMv7 Processor"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .globl cpu_v7_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .equ cpu_v7_suspend_size, 4 * 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ENTRY(cpu_v7_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) stmfd sp!, {r4 - r11, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) stmia r0!, {r4 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mrc p15, 0, r6, c3, c0, 0 @ Domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mrrc p15, 1, r5, r7, c2 @ TTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mrc p15, 0, r7, c2, c0, 1 @ TTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mrc p15, 0, r11, c2, c0, 2 @ TTB control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mrc p15, 0, r8, c1, c0, 0 @ Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) stmia r0, {r5 - r11}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ldmfd sp!, {r4 - r11, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ENDPROC(cpu_v7_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ENTRY(cpu_v7_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ldmia r0!, {r4 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ldmia r0, {r5 - r11}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mcr p15, 0, r6, c3, c0, 0 @ Domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mcrr p15, 0, r1, ip, c2 @ TTB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mcrr p15, 1, r5, r7, c2 @ TTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mcr p15, 0, r1, c2, c0, 0 @ TTB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mcr p15, 0, r7, c2, c0, 1 @ TTB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mcr p15, 0, r11, c2, c0, 2 @ TTB control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ldr r4, =PRRR @ PRRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ldr r5, =NMRR @ NMRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mcr p15, 0, r4, c10, c2, 0 @ write PRRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mcr p15, 0, r5, c10, c2, 1 @ write NMRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) teq r4, r9 @ Is it already set?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mov r0, r8 @ control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) b cpu_resume_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ENDPROC(cpu_v7_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .globl cpu_ca9mp_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ENTRY(cpu_ca9mp_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) stmfd sp!, {r4 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mrc p15, 0, r5, c15, c0, 0 @ Power register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) stmia r0!, {r4 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ldmfd sp!, {r4 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) b cpu_v7_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ENDPROC(cpu_ca9mp_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ENTRY(cpu_ca9mp_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ldmia r0!, {r4 - r5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) teq r4, r10 @ Already restored?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mrc p15, 0, r10, c15, c0, 0 @ Read Power register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) teq r5, r10 @ Already restored?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) b cpu_v7_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ENDPROC(cpu_ca9mp_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifdef CONFIG_CPU_PJ4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) globl_equ cpu_pj4b_reset, cpu_v7_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_PJ4B_ERRATA_4742
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ENTRY(cpu_pj4b_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dsb @ WFI may enter a low-power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dsb @barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ENDPROC(cpu_pj4b_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ENTRY(cpu_pj4b_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) stmfd sp!, {r6 - r10}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) stmia r0!, {r6 - r10}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ldmfd sp!, {r6 - r10}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) b cpu_v7_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ENDPROC(cpu_pj4b_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ENTRY(cpu_pj4b_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ldmia r0!, {r6 - r10}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) b cpu_v7_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ENDPROC(cpu_pj4b_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .globl cpu_pj4b_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * __v7_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Initialise TLB, Caches, and MMU state ready to switch the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * on. Return in r0 the new CP15 C1 control register setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * r4: TTBR0 (low word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * r5: TTBR0 (high word if LPAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * r8: TTBR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * r9: Main ID register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * This should be able to cover all ARMv7 cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * It is assumed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * - cache type register is implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __v7_ca5mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __v7_ca9mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __v7_cr7mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __v7_cr8mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) b 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __v7_ca7mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __v7_ca12mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __v7_ca15mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __v7_b15mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __v7_ca17mp_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mov r10, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 1: adr r0, __v7_setup_stack_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ldr r12, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) add r12, r12, r0 @ the local stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bl v7_invalidate_l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ldmia r12, {r1-r6, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ALT_UP(mov r0, r10) @ fake it for UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) orr r10, r10, r0 @ Set required bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) teq r10, r0 @ Were they already set?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mcrne p15, 0, r10, c1, c0, 1 @ No, update register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) b __v7_setup_cont
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * r0, r10 available for use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * r1, r2, r4, r5, r9, r13: must be preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * r3: contains MIDR rX number in bits 23-20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * r6: contains MIDR rXpY as 8-bit XY number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * r9: MIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __ca8_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) teq r3, #0x00100000 @ only present in r1p*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) orreq r0, r0, #(1 << 6) @ set IBE to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef CONFIG_ARM_ERRATA_458693
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) teq r6, #0x20 @ only present in r2p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) orreq r0, r0, #(1 << 5) @ set L1NEON to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CONFIG_ARM_ERRATA_460075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) teq r6, #0x20 @ only present in r2p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tsteq r0, #1 << 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) b __errata_finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __ca9_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #ifdef CONFIG_ARM_ERRATA_742230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cmp r6, #0x22 @ only present up to r2p2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) orrle r0, r0, #1 << 4 @ set bit #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #ifdef CONFIG_ARM_ERRATA_742231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) teq r6, #0x20 @ present in r2p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) teqne r6, #0x21 @ present in r2p1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) teqne r6, #0x22 @ present in r2p2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) orreq r0, r0, #1 << 12 @ set bit #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) orreq r0, r0, #1 << 22 @ set bit #22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #ifdef CONFIG_ARM_ERRATA_743622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) teq r3, #0x00200000 @ only present in r2p*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) orreq r0, r0, #1 << 6 @ set bit #6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ALT_UP_B(1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) orrlt r0, r0, #1 << 11 @ set bit #11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) b __errata_finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __ca15_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #ifdef CONFIG_ARM_ERRATA_773022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cmp r6, #0x4 @ only present up to r0p4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) orrle r0, r0, #1 << 1 @ disable loop buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) b __errata_finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __ca12_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #ifdef CONFIG_ARM_ERRATA_818325_852422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) orr r10, r10, #1 << 12 @ set bit #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifdef CONFIG_ARM_ERRATA_821420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) orr r10, r10, #1 << 1 @ set bit #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef CONFIG_ARM_ERRATA_825619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) orr r10, r10, #1 << 24 @ set bit #24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #ifdef CONFIG_ARM_ERRATA_857271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) orr r10, r10, #3 << 10 @ set bits #10 and #11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) b __errata_finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) __ca17_errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef CONFIG_ARM_ERRATA_852421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cmp r6, #0x12 @ only present up to r1p2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) orrle r10, r10, #1 << 24 @ set bit #24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #ifdef CONFIG_ARM_ERRATA_852423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cmp r6, #0x12 @ only present up to r1p2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) orrle r10, r10, #1 << 12 @ set bit #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #ifdef CONFIG_ARM_ERRATA_857272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) orr r10, r10, #3 << 10 @ set bits #10 and #11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) b __errata_finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __v7_pj4b_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #ifdef CONFIG_CPU_PJ4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Auxiliary Debug Modes Control 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Auxiliary Debug Modes Control 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Auxiliary Functional Modes Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Auxiliary Debug Modes Control 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Auxiliary Debug Modes Control 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mrc p15, 1, r0, c15, c1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) orr r0, r0, #PJ4B_CLEAN_LINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) orr r0, r0, #PJ4B_INTER_PARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bic r0, r0, #PJ4B_STATIC_BP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mcr p15, 1, r0, c15, c1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Auxiliary Debug Modes Control 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mrc p15, 1, r0, c15, c1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bic r0, r0, #PJ4B_FAST_LDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) orr r0, r0, #PJ4B_AUX_DBG_CTRL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mcr p15, 1, r0, c15, c1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Auxiliary Functional Modes Control Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mrc p15, 1, r0, c15, c2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) orr r0, r0, #PJ4B_SMP_CFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) orr r0, r0, #PJ4B_L1_PAR_CHK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) orr r0, r0, #PJ4B_BROADCAST_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mcr p15, 1, r0, c15, c2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Auxiliary Debug Modes Control 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mrc p15, 1, r0, c15, c1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) orr r0, r0, #PJ4B_WFI_WFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mcr p15, 1, r0, c15, c1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif /* CONFIG_CPU_PJ4B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __v7_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) adr r0, __v7_setup_stack_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ldr r12, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) add r12, r12, r0 @ the local stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bl v7_invalidate_l1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ldmia r12, {r1-r6, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __v7_setup_cont:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) and r0, r9, #0xff000000 @ ARM?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) teq r0, #0x41000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bne __errata_finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) and r3, r9, #0x00f00000 @ variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) and r6, r9, #0x0000000f @ revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) orr r6, r6, r3, lsr #20-4 @ combine variant and revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ubfx r0, r9, #4, #12 @ primary part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Cortex-A8 Errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ldr r10, =0x00000c08 @ Cortex-A8 primary part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) teq r0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) beq __ca8_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Cortex-A9 Errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ldr r10, =0x00000c09 @ Cortex-A9 primary part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) teq r0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) beq __ca9_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Cortex-A12 Errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ldr r10, =0x00000c0d @ Cortex-A12 primary part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) teq r0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) beq __ca12_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Cortex-A17 Errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ldr r10, =0x00000c0e @ Cortex-A17 primary part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) teq r0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) beq __ca17_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Cortex-A15 Errata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ldr r10, =0x00000c0f @ Cortex-A15 primary part number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) teq r0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) beq __ca15_errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) __errata_finish:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mov r10, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ldr r3, =PRRR @ PRRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ldr r6, =NMRR @ NMRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mcr p15, 0, r3, c10, c2, 0 @ write PRRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mcr p15, 0, r6, c10, c2, 1 @ write NMRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dsb @ Complete invalidations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #ifndef CONFIG_ARM_THUMBEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) and r0, r0, #(0xf << 12) @ ThumbEE enabled field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) teq r0, #(1 << 12) @ check if ThumbEE is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mov r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mrc p14, 6, r0, c0, c0, 0 @ load TEECR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) orr r0, r0, #1 @ set the 1st bit in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) adr r3, v7_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ldmia r3, {r3, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #ifdef CONFIG_SWP_EMULATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) orr r3, r3, #(1 << 10) @ set SW bit in "clear"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bic r6, r6, #(1 << 10) @ clear it in "mmuset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mrc p15, 0, r0, c1, c0, 0 @ read control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bic r0, r0, r3 @ clear bits them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) orr r0, r0, r6 @ set them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret lr @ return to head.S:__ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) __v7_setup_stack_ptr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .word PHYS_RELATIVE(__v7_setup_stack, .)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ENDPROC(__v7_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .bss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __v7_setup_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .space 4 * 7 @ 7 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .weak cpu_v7_bugs_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) @ generic v7 bpiall on context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) globl_equ cpu_v7_bpiall_proc_init, cpu_v7_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) globl_equ cpu_v7_bpiall_proc_fin, cpu_v7_proc_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) globl_equ cpu_v7_bpiall_reset, cpu_v7_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) globl_equ cpu_v7_bpiall_do_idle, cpu_v7_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) globl_equ cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) globl_equ cpu_v7_bpiall_set_pte_ext, cpu_v7_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) globl_equ cpu_v7_bpiall_suspend_size, cpu_v7_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) globl_equ cpu_v7_bpiall_do_suspend, cpu_v7_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) globl_equ cpu_v7_bpiall_do_resume, cpu_v7_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) @ Cortex-A8 - always needs bpiall switch_mm implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) globl_equ cpu_ca8_reset, cpu_v7_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) globl_equ cpu_ca8_switch_mm, cpu_v7_bpiall_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) @ Cortex-A9 - needs more registers preserved across suspend/resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) @ and bpiall switch_mm for hardening
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) globl_equ cpu_ca9mp_reset, cpu_v7_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) globl_equ cpu_ca9mp_switch_mm, cpu_v7_bpiall_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) @ Cortex-A15 - needs iciallu switch_mm for hardening
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) globl_equ cpu_ca15_proc_init, cpu_v7_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) globl_equ cpu_ca15_proc_fin, cpu_v7_proc_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) globl_equ cpu_ca15_reset, cpu_v7_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) globl_equ cpu_ca15_do_idle, cpu_v7_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) globl_equ cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) globl_equ cpu_ca15_switch_mm, cpu_v7_iciallu_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) globl_equ cpu_ca15_switch_mm, cpu_v7_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) globl_equ cpu_ca15_set_pte_ext, cpu_v7_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) globl_equ cpu_ca15_do_resume, cpu_v7_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #ifdef CONFIG_CPU_PJ4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) string cpu_arch_name, "armv7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) string cpu_elf_name, "v7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Standard v7 proc info content
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) initfn \initfunc, \name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) HWCAP_EDSP | HWCAP_TLS | \hwcaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .long cpu_v7_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .long \proc_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .long v7wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .long v6_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .long \cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * ARM Ltd. Cortex A5 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .type __v7_ca5mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __v7_ca5mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .long 0x410fc050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * ARM Ltd. Cortex A9 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .type __v7_ca9mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __v7_ca9mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .long 0x410fc090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * ARM Ltd. Cortex A8 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .type __v7_ca8_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __v7_ca8_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .long 0x410fc080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #endif /* CONFIG_ARM_LPAE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Marvell PJ4B processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #ifdef CONFIG_CPU_PJ4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .type __v7_pj4b_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __v7_pj4b_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .long 0x560f5800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .long 0xff0fff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * ARM Ltd. Cortex R7 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .type __v7_cr7mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __v7_cr7mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .long 0x410fc170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * ARM Ltd. Cortex R8 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .type __v7_cr8mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __v7_cr8mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .long 0x410fc180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .size __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * ARM Ltd. Cortex A7 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .type __v7_ca7mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) __v7_ca7mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .long 0x410fc070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * ARM Ltd. Cortex A12 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .type __v7_ca12mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) __v7_ca12mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .long 0x410fc0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * ARM Ltd. Cortex A15 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .type __v7_ca15mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __v7_ca15mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .long 0x410fc0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * Broadcom Corporation Brahma-B15 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .type __v7_b15mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __v7_b15mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .long 0x420f00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions, cache_fns = b15_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * ARM Ltd. Cortex A17 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .type __v7_ca17mp_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) __v7_ca17mp_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .long 0x410fc0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* ARM Ltd. Cortex A73 processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .type __v7_ca73_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) __v7_ca73_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .long 0x410fd090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .size __v7_ca73_proc_info, . - __v7_ca73_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* ARM Ltd. Cortex A75 processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .type __v7_ca75_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __v7_ca75_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .long 0x410fd0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .size __v7_ca75_proc_info, . - __v7_ca75_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * Qualcomm Inc. Krait processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .type __krait_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __krait_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .long 0x510f0400 @ Required ID value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .long 0xff0ffc00 @ Mask for ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Some Krait processors don't indicate support for SDIV and UDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * instructions in the ARM instruction set, even though they actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * do support them. They also don't indicate support for fused multiply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * instructions even though they actually do support them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .size __krait_proc_info, . - __krait_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * Match any ARMv7 processor core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .type __v7_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) __v7_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .long 0x000f0000 @ Required ID value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .long 0x000f0000 @ Mask for ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __v7_proc __v7_proc_info, __v7_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .size __v7_proc_info, . - __v7_proc_info
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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