^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mm/proc-v7-3level.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Catalin Marinas <catalin.marinas@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on arch/arm/mm/proc-v7-2level.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TTB_IRGN_NC (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TTB_IRGN_WBWA (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TTB_IRGN_WT (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TTB_IRGN_WB (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TTB_RGN_NC (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TTB_RGN_OC_WBWA (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TTB_RGN_OC_WT (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TTB_RGN_OC_WB (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TTB_S (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TTB_EAE (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PMD_FLAGS_UP (PMD_SECT_WB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define rpgdl r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define rpgdh r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define rpgdl r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define rpgdh r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * cpu_v7_switch_mm(pgd_phys, tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Set the translation table base pointer to be pgd_phys (physical address of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * the new TTB).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ENTRY(cpu_v7_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mmid r2, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) asid r2, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ENDPROC(cpu_v7_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define rl r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define rh r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define rl r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define rh r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * cpu_v7_set_pte_ext(ptep, pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Set a level 2 translation table entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * - ptep - pointer to level 3 translation table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - pte - PTE value to store (64-bit in r2 and r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ENTRY(cpu_v7_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tst rl, #L_PTE_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) beq 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tst rh, #1 << (57 - 32) @ L_PTE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bicne rl, #L_PTE_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) eor ip, rh, #1 << (55 - 32) @ toggle L_PTE_DIRTY in temp reg to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) @ test for !L_PTE_DIRTY || L_PTE_RDONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tst ip, #1 << (55 - 32) | 1 << (58 - 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) orrne rl, #PTE_AP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) biceq rl, #PTE_AP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 1: strd r2, r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ALT_SMP(W(nop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ENDPROC(cpu_v7_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Memory region attributes for LPAE (defined in pgtable-3level.h):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * n = AttrIndx[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * n MAIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * UNCACHED 000 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * BUFFERABLE 001 01000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * DEV_WC 001 01000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * WRITETHROUGH 010 10101010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * WRITEBACK 011 11101110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * DEV_CACHED 011 11101110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * DEV_SHARED 100 00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * DEV_NONSHARED 100 00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * unused 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * unused 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * WRITEALLOC 111 11111111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .equ PRRR, 0xeeaa4400 @ MAIR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .equ NMRR, 0xff000004 @ MAIR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Macro for setting up the TTBRx and TTBCR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * - \ttbr1 updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mov \tmp, #TTB_EAE @ for TTB control egister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * otherwise booting secondary CPUs would end up using TTBR1 for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * identity mapping set up in TTBR0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mov \tmp, \ttbr1, lsr #20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mov \ttbr1, \ttbr1, lsl #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) addls \ttbr1, \ttbr1, #TTBR1_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * AT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * TFR EV X F IHD LR S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 11 0 110 0 0011 1100 .111 1101 < we want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .type v7_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) v7_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) crval clear=0x0122c302, mmuset=0x30c03c7d, ucset=0x00c01c7c
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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