^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mm/proc-v7-2level.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define TTB_S (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define TTB_RGN_NC (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TTB_RGN_OC_WBWA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TTB_RGN_OC_WT (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TTB_RGN_OC_WB (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TTB_NOS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMD_FLAGS_UP PMD_SECT_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * cpu_v7_switch_mm(pgd_phys, tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Set the translation table base pointer to be pgd_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - pgd_phys - physical address of new TTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * It is assumed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - we are not using split page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Note that we always need to flush BTAC/BTB if IBE is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * even on Cortex-A8 revisions not affected by 430973.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * If IBE is not set, the flush BTAC/BTB won't do anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ENTRY(cpu_v7_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mmid r1, r1 @ get mm->context.id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_PID_IN_CONTEXTIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mrc p15, 0, r2, c13, c0, 1 @ read current context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) lsr r2, r2, #8 @ extract the PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) bfi r1, r2, #8, #24 @ insert into new context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef CONFIG_ARM_ERRATA_754322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) dsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mcr p15, 0, r1, c13, c0, 1 @ set context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bx lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ENDPROC(cpu_v7_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * cpu_v7_set_pte_ext(ptep, pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Set a level 2 translation table entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * - ptep - pointer to level 2 translation table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * (hardware version is stored at +2048 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - pte - PTE value to store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * - ext - value for extended PTE bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ENTRY(cpu_v7_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) str r1, [r0] @ linux version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bic r3, r1, #0x000003f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bic r3, r3, #PTE_TYPE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) orr r3, r3, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) orr r3, r3, #PTE_EXT_AP0 | 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tst r1, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) orrne r3, r3, #PTE_EXT_TEX(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) eor r1, r1, #L_PTE_DIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) orrne r3, r3, #PTE_EXT_APX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tst r1, #L_PTE_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) orrne r3, r3, #PTE_EXT_AP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tst r1, #L_PTE_XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) orrne r3, r3, #PTE_EXT_XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tst r1, #L_PTE_YOUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tstne r1, #L_PTE_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) eorne r1, r1, #L_PTE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tstne r1, #L_PTE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) moveq r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ARM( str r3, [r0, #2048]! )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) THUMB( add r0, r0, #2048 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) THUMB( str r3, [r0] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ALT_SMP(W(nop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bx lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ENDPROC(cpu_v7_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Memory region attributes with SCTLR.TRE=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * n = TEX[0],C,B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * TR = PRRR[2n+1:2n] - memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * IR = NMRR[2n+1:2n] - inner cacheable property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * OR = NMRR[2n+17:2n+16] - outer cacheable property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * n TR IR OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * UNCACHED 000 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * BUFFERABLE 001 10 00 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * WRITETHROUGH 010 10 10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * WRITEBACK 011 10 11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * reserved 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * WRITEALLOC 111 10 01 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * DEV_SHARED 100 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * DEV_NONSHARED 100 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * DEV_WC 001 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * DEV_CACHED 011 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Other attributes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * DS0 = PRRR[16] = 0 - device shareable property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * DS1 = PRRR[17] = 1 - device shareable property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * NS0 = PRRR[18] = 0 - normal shareable property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * NS1 = PRRR[19] = 1 - normal shareable property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * NOS = PRRR[24+n] = 1 - not outer shareable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .equ PRRR, 0xff0a81a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .equ NMRR, 0x40e040e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Macro for setting up the TTBRx and TTBCR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * - \ttb0 and \ttb1 updated with the corresponding flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* AT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * TFR EV X F I D LR S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * 01 0 110 0011 1100 .111 1101 < we want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .type v7_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) v7_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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