^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/proc-v6.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Modified by Catalin Marinas for noMMU support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This is the "shell" of the ARMv6 processor support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define D_CACHE_LINE_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TTB_C (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TTB_S (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TTB_IMP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TTB_RGN_NC (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TTB_RGN_WBWA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TTB_RGN_WT (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TTB_RGN_WB (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TTB_FLAGS_UP TTB_RGN_WBWA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PMD_FLAGS_UP PMD_SECT_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ENTRY(cpu_v6_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ENTRY(cpu_v6_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mrc p15, 0, r0, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bic r0, r0, #0x1000 @ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bic r0, r0, #0x0006 @ .............ca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * cpu_v6_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Perform a soft reset of the system. Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * - loc - location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ENTRY(cpu_v6_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mrc p15, 0, r1, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bic r1, r1, #0x1 @ ...............m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mcr p15, 0, r1, c1, c0, 0 @ disable MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mov r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mcr p15, 0, r1, c7, c5, 4 @ ISB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ENDPROC(cpu_v6_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * cpu_v6_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Idle the processor (eg, wait for interrupt).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * IRQs are already disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ENTRY(cpu_v6_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mov r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ENTRY(cpu_v6_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) add r0, r0, #D_CACHE_LINE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) subs r1, r1, #D_CACHE_LINE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bhi 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * cpu_v6_switch_mm(pgd_phys, tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Set the translation table base pointer to be pgd_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * - pgd_phys - physical address of new TTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * It is assumed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * - we are not using split page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ENTRY(cpu_v6_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mov r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mmid r1, r1 @ get mm->context.id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_PID_IN_CONTEXTIDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mrc p15, 0, r2, c13, c0, 1 @ read current context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bic r2, r2, #0xff @ extract the PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) and r1, r1, #0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) orr r1, r1, r2 @ insert into new context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mcr p15, 0, r1, c13, c0, 1 @ set context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * cpu_v6_set_pte_ext(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Set a level 2 translation table entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * - ptep - pointer to level 2 translation table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * (hardware version is stored at -1024 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * - pte - PTE value to store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * - ext - value for extended PTE bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) armv6_mt_table cpu_v6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ENTRY(cpu_v6_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) armv6_set_pte_ext cpu_v6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .globl cpu_v6_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .equ cpu_v6_suspend_size, 4 * 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ENTRY(cpu_v6_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) stmfd sp!, {r4 - r9, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mrc p15, 0, r5, c3, c0, 0 @ Domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mrc p15, 0, r9, c1, c0, 0 @ control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) stmia r0, {r4 - r9}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ldmfd sp!, {r4- r9, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ENDPROC(cpu_v6_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ENTRY(cpu_v6_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ldmia r0, {r4 - r9}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mcr p15, 0, r5, c3, c0, 0 @ Domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mcr p15, 0, ip, c2, c0, 2 @ TTB control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mcr p15, 0, ip, c7, c5, 4 @ ISB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mov r0, r9 @ control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) b cpu_resume_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ENDPROC(cpu_v6_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) string cpu_v6_name, "ARMv6-compatible processor"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * __v6_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Initialise TLB, Caches, and MMU state ready to switch the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * on. Return in r0 the new CP15 C1 control register setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * We automatically detect if we have a Harvard cache, and use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Harvard cache control instructions insead of the unified cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * control instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * This should be able to cover all ARMv6 cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * It is assumed that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * - cache type register is implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __v6_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ALT_UP(nop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) orr r0, r0, #0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ALT_UP(nop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mcr p15, 0, r0, c2, c0, 2 @ TTB control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mcr p15, 0, r8, c2, c0, 1 @ load TTB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) @ complete invalidations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) adr r5, v6_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ldmia r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mrc p15, 0, r0, c1, c0, 0 @ read control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) bic r0, r0, r5 @ clear bits them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) orr r0, r0, r6 @ set them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef CONFIG_ARM_ERRATA_364296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * corruption with hit-under-miss enabled). The conditional code below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * (setting the undocumented bit 31 in the auxiliary control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * and the FI bit in the control register) disables hit-under-miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * without putting the processor into full low interrupt latency mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ldr r6, =0x4107b362 @ id for ARM1136 r0p2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mrc p15, 0, r5, c0, c0, 0 @ get processor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) teq r5, r6 @ check for the faulty core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret lr @ return to head.S:__ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * V X F I D LR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * 0 110 0011 1.00 .111 1101 < we want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .type v6_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) v6_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) string cpu_arch_name, "armv6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) string cpu_elf_name, "v6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Match any ARMv6 processor core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .type __v6_proc_info, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __v6_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .long 0x0007b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .long 0x0007f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ALT_SMP(.long \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PMD_SECT_AP_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PMD_FLAGS_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ALT_UP(.long \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PMD_SECT_AP_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PMD_FLAGS_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PMD_SECT_XN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) initfn __v6_setup, __v6_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* See also feat_v6_fixup() for HWCAP_TLS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .long cpu_v6_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .long v6_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .long v6wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .long v6_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .long v6_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .size __v6_proc_info, . - __v6_proc_info
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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