Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-sa1100.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 1997-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  MMU functions for SA110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  functions on the StrongARM-1100 and StrongARM-1110.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  Note that SA1100 and SA1110 share everything but their name and CPU ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *    Flush the read buffer at context switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * the cache line size of the I and D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DCACHELINESIZE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.section .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * cpu_sa1100_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) ENTRY(cpu_sa1100_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	mcr	p15, 0, r0, c9, c0, 5		@ Allow read-buffer operations from userland
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * cpu_sa1100_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * Prepare the CPU for reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *  - Disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *  - Clean and turn off caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) ENTRY(cpu_sa1100_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	mcr	p15, 0, ip, c15, c2, 2		@ Disable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	bic	r0, r0, #0x1000			@ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	bic	r0, r0, #0x000e			@ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * cpu_sa1100_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * Perform a soft reset of the system.  Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) ENTRY(cpu_sa1100_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	bic	ip, ip, #0x000f			@ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	bic	ip, ip, #0x1100			@ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) ENDPROC(cpu_sa1100_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * cpu_sa1100_do_idle(type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * Cause the processor to idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * type: call type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *   0 = slow idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  *   1 = fast idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *   2 = switch to slow processor clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *   3 = switch to fast processor clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) ENTRY(cpu_sa1100_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mov	r0, r0				@ 4 nop padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mov	r0, r0				@ 4 nop padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ldr	r1, =UNCACHEABLE_ADDR		@ ptr to uncacheable address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	@ --- aligned to a cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mcr	p15, 0, r0, c15, c2, 2		@ disable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ldr	r1, [r1, #0]			@ force switch to MCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mcr	p15, 0, r0, c15, c8, 2		@ wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* ================================= CACHE ================================ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * cpu_sa1100_dcache_clean_area(addr,sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Clean the specified entry of any caches such that the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * translation fetches will obtain correct data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * addr: cache-unaligned virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ENTRY(cpu_sa1100_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	add	r0, r0, #DCACHELINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	subs	r1, r1, #DCACHELINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * cpu_sa1100_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ENTRY(cpu_sa1100_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	str	lr, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	bl	v4wb_flush_kern_cache_all	@ clears IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ldr	pc, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * cpu_sa1100_set_pte_ext(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ENTRY(cpu_sa1100_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	armv3_set_pte_ext wc_disable=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .globl	cpu_sa1100_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .equ	cpu_sa1100_suspend_size, 4 * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ENTRY(cpu_sa1100_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	stmfd	sp!, {r4 - r6, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mrc	p15, 0, r4, c3, c0, 0		@ domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	mrc	p15, 0, r5, c13, c0, 0		@ PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	mrc	p15, 0, r6, c1, c0, 0		@ control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	stmia	r0, {r4 - r6}			@ store cp regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	ldmfd	sp!, {r4 - r6, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ENDPROC(cpu_sa1100_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ENTRY(cpu_sa1100_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ldmia	r0, {r4 - r6}			@ load cp regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mcr	p15, 0, ip, c8, c7, 0		@ flush I+D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mcr	p15, 0, ip, c7, c7, 0		@ flush I&D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	mcr	p15, 0, r4, c3, c0, 0		@ domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	mcr	p15, 0, r1, c2, c0, 0		@ translation table base addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	mcr	p15, 0, r5, c13, c0, 0		@ PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	mov	r0, r6				@ control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	b	cpu_resume_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ENDPROC(cpu_sa1100_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.type	__sa1100_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __sa1100_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	adr	r5, sa1100_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	ldmia	r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mrc	p15, 0, r0, c1, c0		@ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	orr	r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.size	__sa1100_setup, . - __sa1100_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 *  R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * ..11 0001 ..11 1101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.type	sa1100_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sa1100_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	crval	clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * SA1100 and SA1110 share the same function calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	string	cpu_arch_name, "armv4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	string	cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	string	cpu_sa1100_name, "StrongARM-1100"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	string	cpu_sa1110_name, "StrongARM-1110"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.type	__\name\()_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __\name\()_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.long	\cpu_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.long	\cpu_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	initfn	__sa1100_setup, __\name\()_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.long	\cpu_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.long	sa1100_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.long	v4wb_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.long	v4_mc_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.long	v4wb_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.size	__\name\()_proc_info, . - __\name\()_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name