Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-sa110.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 1997-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  MMU functions for SA110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  functions on the StrongARM-110.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * the cache line size of the I and D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DCACHELINESIZE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * cpu_sa110_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) ENTRY(cpu_sa110_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * cpu_sa110_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) ENTRY(cpu_sa110_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mcr	p15, 0, r0, c15, c2, 2		@ Disable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	bic	r0, r0, #0x1000			@ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	bic	r0, r0, #0x000e			@ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * cpu_sa110_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * Perform a soft reset of the system.  Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) ENTRY(cpu_sa110_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	bic	ip, ip, #0x000f			@ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	bic	ip, ip, #0x1100			@ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) ENDPROC(cpu_sa110_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * cpu_sa110_do_idle(type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * Cause the processor to idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * type: call type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *   0 = slow idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *   1 = fast idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *   2 = switch to slow processor clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *   3 = switch to fast processor clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) ENTRY(cpu_sa110_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mcr	p15, 0, ip, c15, c2, 2		@ disable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ldr	r1, =UNCACHEABLE_ADDR		@ load from uncacheable loc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ldr	r1, [r1, #0]			@ force switch to MCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mcr	p15, 0, r0, c15, c8, 2		@ Wait for interrupt, cache aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	mov	r0, r0				@ safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* ================================= CACHE ================================ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * cpu_sa110_dcache_clean_area(addr,sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * Clean the specified entry of any caches such that the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * translation fetches will obtain correct data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * addr: cache-unaligned virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ENTRY(cpu_sa110_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	add	r0, r0, #DCACHELINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	subs	r1, r1, #DCACHELINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * cpu_sa110_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ENTRY(cpu_sa110_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	str	lr, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	bl	v4wb_flush_kern_cache_all	@ clears IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ldr	pc, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * cpu_sa110_set_pte_ext(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ENTRY(cpu_sa110_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	armv3_set_pte_ext wc_disable=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.type	__sa110_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __sa110_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mov	r10, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	adr	r5, sa110_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ldmia	r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	mrc	p15, 0, r0, c1, c0		@ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	orr	r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.size	__sa110_setup, . - __sa110_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 *  R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * ..01 0001 ..11 1101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.type	sa110_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sa110_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	crval	clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	string	cpu_arch_name, "armv4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	string	cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	string	cpu_sa110_name, "StrongARM-110"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.type	__sa110_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __sa110_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.long	0x4401a100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.long	0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	initfn	__sa110_setup, __sa110_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.long	cpu_sa110_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.long	sa110_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.long	v4wb_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.long	v4wb_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.long	v4wb_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.size	__sa110_proc_info, . - __sa110_proc_info