Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Heavily based on proc-arm926.S and proc-xsc3.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * This is the maximum size of an area which will be flushed.  If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * area is larger than this, then we flush the whole cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CACHE_DLIMIT	32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * The cache line size of the L1 D cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CACHE_DLINESIZE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * cpu_mohawk_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) ENTRY(cpu_mohawk_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * cpu_mohawk_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) ENTRY(cpu_mohawk_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	bic	r0, r0, #0x1800			@ ...iz...........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	bic	r0, r0, #0x0006			@ .............ca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * cpu_mohawk_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Perform a soft reset of the system.  Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) ENTRY(cpu_mohawk_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	bic	ip, ip, #0x0007			@ .............cam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	bic	ip, ip, #0x1100			@ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) ENDPROC(cpu_mohawk_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * cpu_mohawk_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * Called with IRQs disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) ENTRY(cpu_mohawk_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	mcr	p15, 0, r0, c7, c0, 4		@ wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *	flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *	Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) ENTRY(mohawk_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) ENDPROC(mohawk_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *	flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *	Clean and invalidate all cache entries in a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  *	address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ENTRY(mohawk_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  *	flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  *	Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ENTRY(mohawk_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mov	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __flush_whole_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mcr	p15, 0, ip, c7, c14, 0		@ clean & invalidate all D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mcrne	p15, 0, ip, c7, c10, 0		@ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *	flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *	Clean and invalidate a range of cache entries in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *	specified address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	- start	- start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *	- end	- end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *	- flags	- vm_flags describing address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ENTRY(mohawk_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	sub	r3, r1, r0			@ calculate total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	cmp	r3, #CACHE_DLIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	bgt	__flush_whole_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 1:	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *	coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *	Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  *	region described by start, end.  If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  *	Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ENTRY(mohawk_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  *	Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  *	region described by start, end.  If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  *	Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ENTRY(mohawk_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *	flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *	Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  *	the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  *	- addr	- kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *	- size	- region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ENTRY(mohawk_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	add	r1, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  *	dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  *	Invalidate (discard) the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  *	May not write back any entries.  If 'start' or 'end'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *	are not cache line aligned, those lines must be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  *	back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mohawk_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	tst	r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	tst	r1, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  *	dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  *	Clean the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mohawk_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *	dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  *	Clean and invalidate the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ENTRY(mohawk_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *	dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  *	- start	- kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *	- size	- size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  *	- dir	- DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ENTRY(mohawk_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	add	r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	cmp	r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	beq	mohawk_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	bcs	mohawk_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	b	mohawk_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ENDPROC(mohawk_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  *	dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  *	- start	- kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  *	- size	- size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  *	- dir	- DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ENTRY(mohawk_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ENDPROC(mohawk_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.globl	mohawk_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.equ	mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	define_cache_functions mohawk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ENTRY(cpu_mohawk_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	subs	r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * cpu_mohawk_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ENTRY(cpu_mohawk_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	mcr	p15, 0, ip, c7, c14, 0		@ clean & invalidate all D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	orr	r0, r0, #0x18			@ cache the page table in L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)  * cpu_mohawk_set_pte_ext(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ENTRY(cpu_mohawk_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	armv3_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .globl	cpu_mohawk_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .equ	cpu_mohawk_suspend_size, 4 * 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ENTRY(cpu_mohawk_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	stmfd	sp!, {r4 - r9, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	mrc	p14, 0, r4, c6, c0, 0	@ clock configuration, for turbo mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	mrc	p15, 0, r5, c15, c1, 0	@ CP access reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	mrc	p15, 0, r6, c13, c0, 0	@ PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	mrc 	p15, 0, r7, c3, c0, 0	@ domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	mrc	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	mrc 	p15, 0, r9, c1, c0, 0	@ control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	bic	r4, r4, #2		@ clear frequency change bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	stmia	r0, {r4 - r9}		@ store cp regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ldmia	sp!, {r4 - r9, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ENDPROC(cpu_mohawk_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ENTRY(cpu_mohawk_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ldmia	r0, {r4 - r9}		@ load cp regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I & D caches, BTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	mcr	p15, 0, ip, c7, c10, 4	@ drain write (&fill) buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	mcr	p15, 0, ip, c7, c5, 4	@ flush prefetch buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	mcr	p14, 0, r4, c6, c0, 0	@ clock configuration, turbo mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	mcr	p15, 0, r5, c15, c1, 0	@ CP access reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	mcr	p15, 0, r6, c13, c0, 0	@ PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	orr	r1, r1, #0x18		@ cache the page table in L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	mov	r0, r9			@ control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	b	cpu_resume_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ENDPROC(cpu_mohawk_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.type	__mohawk_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __mohawk_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	orr	r4, r4, #0x18			@ cache the page table in L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	mov	r0, #0				@ don't allow CP access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	mcr	p15, 0, r0, c15, c1, 0		@ write CP access register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	adr	r5, mohawk_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	ldmia	r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	mrc	p15, 0, r0, c1, c0		@ get control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	orr	r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.size	__mohawk_setup, . - __mohawk_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	 *  R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	 * .011 1001 ..00 0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.type	mohawk_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mohawk_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	crval	clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	string	cpu_arch_name, "armv5te"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	string	cpu_elf_name, "v5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	string	cpu_mohawk_name, "Marvell 88SV331x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.type	__88sv331x_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) __88sv331x_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.long	0x56158000			@ Marvell 88SV331x (MOHAWK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.long	0xfffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	initfn	__mohawk_setup, __88sv331x_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.long	cpu_mohawk_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.long	mohawk_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.long	v4wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.long	v4wb_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.long	mohawk_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.size	__88sv331x_proc_info, . - __88sv331x_proc_info