Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * We need constants.h for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  VMA_VM_MM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  VMA_VM_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifdef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/v7m.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	.macro	vma_vm_mm, rd, rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	ldr	\rd, [\rn, #VMA_VM_MM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * vma_vm_flags - get vma->vm_flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.macro	vma_vm_flags, rd, rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	ldr	\rd, [\rn, #VMA_VM_FLAGS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * act_mm - get current->active_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.macro	act_mm, rd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	get_thread_info \rd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	ldr	\rd, [\rd, #TI_TASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.if (TSK_ACTIVE_MM > IMM12_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	add	\rd, \rd, #TSK_ACTIVE_MM & ~IMM12_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	ldr	\rd, [\rd, #TSK_ACTIVE_MM & IMM12_MASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * mmid - get context id from mm pointer (mm->context.id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * note, this field is 64bit, so in big-endian the two words are swapped too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.macro	mmid, rd, rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #ifdef __ARMEB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ldr	\rd, [\rn, #MM_CONTEXT_ID + 4 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	ldr	\rd, [\rn, #MM_CONTEXT_ID]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * mask_asid - mask the ASID from the context ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.macro	asid, rd, rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	and	\rd, \rn, #255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.macro	crval, clear, mmuset, ucset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.word	\clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.word	\mmuset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.word	\clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.word	\ucset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * dcache_line_size - get the minimum D-cache line size from the CTR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * on ARMv7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.macro	dcache_line_size, reg, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #ifdef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	movw	\tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	movt	\tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ldr     \tmp, [\tmp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	mrc	p15, 0, \tmp, c0, c0, 1		@ read ctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	lsr	\tmp, \tmp, #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	and	\tmp, \tmp, #0xf		@ cache line size encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mov	\reg, #4			@ bytes per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mov	\reg, \reg, lsl \tmp		@ actual cache line size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * icache_line_size - get the minimum I-cache line size from the CTR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * on ARMv7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.macro	icache_line_size, reg, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #ifdef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	movw	\tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	movt	\tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ldr     \tmp, [\tmp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mrc	p15, 0, \tmp, c0, c0, 1		@ read ctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	and	\tmp, \tmp, #0xf		@ cache line size encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	mov	\reg, #4			@ bytes per word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mov	\reg, \reg, lsl \tmp		@ actual cache line size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * Sanity check the PTE configuration for the code below - which makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * certain assumptions about how these bits are laid out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if L_PTE_SHARED != PTE_EXT_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #error PTE shared bit mismatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #if !defined (CONFIG_ARM_LPAE) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	(L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 L_PTE_PRESENT) > L_PTE_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #error Invalid Linux PTE bit settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif	/* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * The ARMv6 and ARMv7 set_pte_ext translation function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * Permission translation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *  YUWD  APX AP1 AP0	SVC	User
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *  0xxx   0   0   0	no acc	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *  100x   1   0   1	r/o	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *  10x0   1   0   1	r/o	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *  1011   0   0   1	r/w	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *  110x   1   1   1	r/o	r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *  11x0   1   1   1	r/o	r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *  1111   0   1   1	r/w	r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.macro	armv6_mt_table pfx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) \pfx\()_mt_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.long	0x00						@ L_PTE_MT_UNCACHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_BUFFERABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.long	PTE_CACHEABLE					@ L_PTE_MT_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.long	PTE_BUFFERABLE					@ L_PTE_MT_DEV_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.long	0x00						@ unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.long	0x00						@ L_PTE_MT_MINICACHE (not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.long	PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE	@ L_PTE_MT_WRITEALLOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.long	0x00						@ unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_DEV_WC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.long	0x00						@ unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_DEV_CACHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.long	PTE_EXT_TEX(2)					@ L_PTE_MT_DEV_NONSHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.long	0x00						@ unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.long	0x00						@ unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.long	PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX	@ L_PTE_MT_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.macro	armv6_set_pte_ext pfx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	str	r1, [r0], #2048			@ linux version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	bic	r3, r1, #0x000003fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	bic	r3, r3, #PTE_TYPE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	orr	r3, r3, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	orr	r3, r3, #PTE_EXT_AP0 | 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	adr	ip, \pfx\()_mt_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	and	r2, r1, #L_PTE_MT_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ldr	r2, [ip, r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	eor	r1, r1, #L_PTE_DIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tst	r1, #L_PTE_DIRTY|L_PTE_RDONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	orrne	r3, r3, #PTE_EXT_APX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tst	r1, #L_PTE_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	orrne	r3, r3, #PTE_EXT_AP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	tstne	r3, #PTE_EXT_APX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	@ user read-only -> kernel read-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	bicne	r3, r3, #PTE_EXT_AP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	tst	r1, #L_PTE_XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	orrne	r3, r3, #PTE_EXT_XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	eor	r3, r3, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	tst	r1, #L_PTE_YOUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	tstne	r1, #L_PTE_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	moveq	r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	tstne	r1, #L_PTE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	movne	r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	str	r3, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * covering most CPUs except Xscale and Xscale 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * Permission translation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *  YUWD   AP	SVC	User
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *  0xxx  0x00	no acc	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *  100x  0x00	r/o	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *  10x0  0x00	r/o	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *  1011  0x55	r/w	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  *  110x  0xaa	r/w	r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  *  11x0  0xaa	r/w	r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *  1111  0xff	r/w	r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.macro	armv3_set_pte_ext wc_disable=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	str	r1, [r0], #2048			@ linux version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	eor	r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	bic	r2, r1, #PTE_SMALL_AP_MASK	@ keep C, B bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	bic	r2, r2, #PTE_TYPE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	orr	r2, r2, #PTE_TYPE_SMALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	tst	r3, #L_PTE_USER			@ user?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	tst	r3, #L_PTE_RDONLY | L_PTE_DIRTY	@ write and dirty?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	tst	r3, #L_PTE_PRESENT | L_PTE_YOUNG	@ present and young?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	movne	r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.if	\wc_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	tst	r2, #PTE_CACHEABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	bicne	r2, r2, #PTE_BUFFERABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	str	r2, [r0]		@ hardware version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * Xscale set_pte_ext translation, split into two halves to cope
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * with work-arounds.  r3 must be preserved by code between these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * two macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * Permission translation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  *  YUWD  AP	SVC	User
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *  0xxx  00	no acc	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  *  100x  00	r/o	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  *  10x0  00	r/o	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  *  1011  01	r/w	no acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  *  110x  10	r/w	r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  *  11x0  10	r/w	r/o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *  1111  11	r/w	r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.macro	xscale_set_pte_ext_prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	str	r1, [r0]			@ linux version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	eor	r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	bic	r2, r1, #PTE_SMALL_AP_MASK	@ keep C, B bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	orr	r2, r2, #PTE_TYPE_EXT		@ extended page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	tst	r3, #L_PTE_USER			@ user?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	orrne	r2, r2, #PTE_EXT_AP_URO_SRW	@ yes -> user r/o, system r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	tst	r3, #L_PTE_RDONLY | L_PTE_DIRTY	@ write and dirty?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	orreq	r2, r2, #PTE_EXT_AP_UNO_SRW	@ yes -> user n/a, system r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 						@ combined with user -> user r/w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.macro	xscale_set_pte_ext_epilogue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	tst	r3, #L_PTE_PRESENT | L_PTE_YOUNG	@ present and young?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	movne	r2, #0				@ no -> fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	str	r2, [r0, #2048]!		@ hardware version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0, bugs=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * If we are building for big.Little with branch predictor hardening,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * we need the processor function tables to remain available after boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.type	\name\()_processor_functions, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ENTRY(\name\()_processor_functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.word	\dabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.word	\pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.word	cpu_\name\()_proc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.word	\bugs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.word	cpu_\name\()_proc_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.word	cpu_\name\()_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.word	cpu_\name\()_do_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.word	cpu_\name\()_dcache_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.word	cpu_\name\()_switch_mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.if \nommu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.word	cpu_\name\()_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.if \suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.word	cpu_\name\()_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.word	cpu_\name\()_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.word	cpu_\name\()_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.word	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.size	\name\()_processor_functions, . - \name\()_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .macro define_cache_functions name:req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.type	\name\()_cache_fns, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ENTRY(\name\()_cache_fns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.long	\name\()_flush_icache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.long	\name\()_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.long   \name\()_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.long	\name\()_flush_user_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.long	\name\()_flush_user_cache_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.long	\name\()_coherent_kern_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.long	\name\()_coherent_user_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	.long	\name\()_flush_kern_dcache_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.long	\name\()_dma_map_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.long	\name\()_dma_unmap_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.long	\name\()_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.size	\name\()_cache_fns, . - \name\()_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .macro define_tlb_functions name:req, flags_up:req, flags_smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.type	\name\()_tlb_fns, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.align 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ENTRY(\name\()_tlb_fns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.long	\name\()_flush_user_tlb_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.long	\name\()_flush_kern_tlb_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.ifnb \flags_smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		ALT_SMP(.long	\flags_smp )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		ALT_UP(.long	\flags_up )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.long	\flags_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.size	\name\()_tlb_fns, . - \name\()_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .macro globl_equ x, y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.globl	\x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.equ	\x, \y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .macro	initfn, func, base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.long	\func - \base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * Macro to calculate the log2 size for the protection region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * registers. This calculates rd = log2(size) - 1.  tmp must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * not be the same register as rd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .macro	pr_sz, rd, size, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	mov	\tmp, \size, lsr #12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	mov	\rd, #11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 1:	movs	\tmp, \tmp, lsr #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	addne	\rd, \rd, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	bne	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * Macro to generate a protection region register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 * given a pre-masked address, size, and enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	 * Corrupts size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .macro	pr_val, dest, addr, size, enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	pr_sz	\dest, \size, \size		@ calculate log2(size) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	orr	\dest, \addr, \dest, lsl #1	@ mask in the region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	orr	\dest, \dest, \enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .endm