Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Written by : Luke Lee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2005 Faraday Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * functions on the fa526.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CACHE_DLINESIZE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * cpu_fa526_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) ENTRY(cpu_fa526_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * cpu_fa526_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) ENTRY(cpu_fa526_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	bic	r0, r0, #0x1000			@ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	bic	r0, r0, #0x000e			@ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * cpu_fa526_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * Perform a soft reset of the system.  Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) ENTRY(cpu_fa526_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* TODO: Use CP8 if possible... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	bic	ip, ip, #0x000f			@ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	bic	ip, ip, #0x1100			@ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	bic	ip, ip, #0x0800			@ BTB off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) ENDPROC(cpu_fa526_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * cpu_fa526_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) ENTRY(cpu_fa526_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) ENTRY(cpu_fa526_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	subs	r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * cpu_fa526_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ENTRY(cpu_fa526_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mcr	p15, 0, ip, c7, c14, 0		@ clean and invalidate whole D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mcr	p15, 0, ip, c7, c5, 6		@ invalidate BTB since mm changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate UTLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * cpu_fa526_set_pte_ext(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.align	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ENTRY(cpu_fa526_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	armv3_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.type	__fa526_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __fa526_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* On return of this routine, r0 must carry correct flags for CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mcr	p15, 0, r0, c7, c5, 5		@ invalidate IScratchpad RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mov	r0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mcr	p15, 0, r0, c1, c1, 0		@ turn-on ECR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mov	r0, #0x1f			@ Domains 0, 1 = manager, 2 = client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	mcr	p15, 0, r0, c3, c0		@ load domain access register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	mrc	p15, 0, r0, c1, c0		@ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ldr	r5, fa526_cr1_clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ldr	r5, fa526_cr1_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	orr	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.size	__fa526_setup, . - __fa526_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * ..11 1001 .111 1101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.type	fa526_cr1_clear, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.type	fa526_cr1_set, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) fa526_cr1_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.word	0x3f3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) fa526_cr1_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.word	0x397D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	string	cpu_arch_name, "armv4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	string	cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	string	cpu_fa526_name, "FA526"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.type	__fa526_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __fa526_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.long	0x66015261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.long	0xff01fff1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	initfn	__fa526_setup, __fa526_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.long	HWCAP_SWP | HWCAP_HALF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.long	cpu_fa526_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.long	fa526_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.long	fa_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.long	fa_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.long	fa_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.size	__fa526_proc_info, . - __fa526_proc_info