Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  (Many of cache codes are from proc-arm926.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * comprising 256 lines of 32 bytes (8 words).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CACHE_DSIZE	(CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CACHE_DLINESIZE	32			/* fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CACHE_DSEGMENTS	4			/* fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CACHE_DENTRIES	(CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CACHE_DLIMIT	(CACHE_DSIZE * 4)	/* benchmark needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * cpu_arm946_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * cpu_arm946_switch_mm()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * These are not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) ENTRY(cpu_arm946_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) ENTRY(cpu_arm946_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * cpu_arm946_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) ENTRY(cpu_arm946_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	bic	r0, r0, #0x00001000		@ i-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	bic	r0, r0, #0x00000004		@ d-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * cpu_arm946_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * Params  : r0 = address to jump to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * Notes   : This sets up everything for a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) ENTRY(cpu_arm946_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mcr	p15, 0, ip, c7, c5, 0		@ flush I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	bic	ip, ip, #0x00000005		@ .............c.p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	bic	ip, ip, #0x00001000		@ i-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) ENDPROC(cpu_arm946_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * cpu_arm946_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) ENTRY(cpu_arm946_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *	flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *	Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) ENTRY(arm946_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) ENDPROC(arm946_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *	flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) ENTRY(arm946_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *	flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *	Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) ENTRY(arm946_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mov	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __flush_whole_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	mov	r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	subs	r3, r3, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	bcs	2b				@ entries n to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	subs	r1, r1, #1 << 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	bcs	1b				@ segments 3 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mcrne	p15, 0, ip, c7, c5, 0		@ flush I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *	Clean and invalidate a range of cache entries in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *	specified address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *	- start	- start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *	- end	- end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	- flags	- vm_flags describing address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ENTRY(arm946_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	sub	r3, r1, r0			@ calculate total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	cmp	r3, #CACHE_DLIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	bhs	__flush_whole_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 1:	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *	coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *	Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *	region described by start, end.  If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *	Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ENTRY(arm946_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *	coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  *	Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *	region described by start, end.  If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  *	Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ENTRY(arm946_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *	flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *	Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *	the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *	- addr	- kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *	- size	- region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ENTRY(arm946_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	add	r1, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *	dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *	Invalidate (discard) the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *	May not write back any entries.  If 'start' or 'end'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  *	are not cache line aligned, those lines must be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  *	back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) arm946_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	tst	r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	tst	r1, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *	dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  *	Clean the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) arm946_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *	dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  *	Clean and invalidate the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * (same as arm926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ENTRY(arm946_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  *	dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  *	- start	- kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  *	- size	- size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  *	- dir	- DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ENTRY(arm946_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	add	r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	cmp	r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	beq	arm946_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	bcs	arm946_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	b	arm946_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ENDPROC(arm946_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  *	dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  *	- start	- kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  *	- size	- size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *	- dir	- DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ENTRY(arm946_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ENDPROC(arm946_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.globl	arm946_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.equ	arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	define_cache_functions arm946
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ENTRY(cpu_arm946_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	subs	r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.type	__arm946_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __arm946_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	mcr	p15, 0, r0, c6, c3, 0		@ disable memory region 3~7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mcr	p15, 0, r0, c6, c4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	mcr	p15, 0, r0, c6, c5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	mcr	p15, 0, r0, c6, c6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	mcr	p15, 0, r0, c6, c7, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	mov	r0, #0x0000003F			@ base = 0, size = 4GB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	ldr	r7, =CONFIG_DRAM_SIZE		@ size of RAM (must be >= 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	pr_val	r3, r0, r7, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	mcr	p15, 0, r3, c6, c1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ldr	r7, =CONFIG_FLASH_SIZE		@ size of FLASH (must be >= 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	pr_val	r3, r0, r7, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	mcr	p15, 0, r3, c6, c2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	mov	r0, #0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	mov	r0, #0x00			@ disable whole write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	mov	r0, #0x02			@ region 1 write bufferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	mcr	p15, 0, r0, c3, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  *  Access Permission Settings for future permission control by PU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  *				priv.	user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * 	region 0 (whole)	rw	--	: b0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  * 	region 1 (RAM)		rw	rw	: b0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * 	region 2 (FLASH)	rw	r-	: b0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  *	region 3~7 (none)	--	--	: b0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	mov	r0, #0x00000031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	orr	r0, r0, #0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	mrc	p15, 0, r0, c1, c0		@ get control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	orr	r0, r0, #0x00001000		@ I-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	orr	r0, r0, #0x00000005		@ MPU/D-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	orr	r0, r0, #0x00004000		@ .1.. .... .... ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.size	__arm946_setup, . - __arm946_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	string	cpu_arch_name, "armv5te"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	string	cpu_elf_name, "v5t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	string	cpu_arm946_name, "ARM946E-S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.type	__arm946_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __arm946_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.long	0x41009460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.long	0xff00fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	initfn	__arm946_setup, __arm946_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.long	cpu_arm946_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.long	arm946_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.long	arm946_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.size	__arm946_proc_info, . - __arm946_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)