^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/arm940.S: utility functions for ARM940T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CACHE_DLINESIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CACHE_DSEGMENTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CACHE_DENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * cpu_arm940_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * cpu_arm940_switch_mm()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * These are not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ENTRY(cpu_arm940_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ENTRY(cpu_arm940_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * cpu_arm940_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ENTRY(cpu_arm940_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) mrc p15, 0, r0, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bic r0, r0, #0x00001000 @ i-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bic r0, r0, #0x00000004 @ d-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * cpu_arm940_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Params : r0 = address to jump to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Notes : This sets up everything for a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ENTRY(cpu_arm940_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mcr p15, 0, ip, c7, c5, 0 @ flush I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mcr p15, 0, ip, c7, c6, 0 @ flush D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mrc p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bic ip, ip, #0x00000005 @ .............c.p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bic ip, ip, #0x00001000 @ i-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mcr p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ret r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ENDPROC(cpu_arm940_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * cpu_arm940_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ENTRY(cpu_arm940_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ENTRY(arm940_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ENDPROC(arm940_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ENTRY(arm940_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ENTRY(arm940_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mov r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * There is no efficient way to flush a range of cache entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * in the specified address range. Thus, flushes all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * - start - start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * - end - end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * - flags - vm_flags describing address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ENTRY(arm940_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mcr p15, 0, ip, c7, c6, 0 @ flush D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) subs r1, r1, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bcs 1b @ segments 3 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * region described by start, end. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ENTRY(arm940_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * region described by start, end. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ENTRY(arm940_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * - addr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * - size - region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ENTRY(arm940_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) subs r1, r1, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * There is no efficient way to invalidate a specifid virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * address range. Thus, invalidates all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) arm940_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) subs r1, r1, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * There is no efficient way to clean a specifid virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * address range. Thus, cleans all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) arm940_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ENTRY(cpu_arm940_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) subs r1, r1, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * There is no efficient way to clean and invalidate a specifid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ENTRY(arm940_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) subs r1, r1, #1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ENTRY(arm940_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) add r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cmp r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) beq arm940_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bcs arm940_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) b arm940_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ENDPROC(arm940_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ENTRY(arm940_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ENDPROC(arm940_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .globl arm940_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .equ arm940_flush_kern_cache_louis, arm940_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) define_cache_functions arm940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .type __arm940_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __arm940_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mcr p15, 0, r0, c6, c4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mcr p15, 0, r0, c6, c5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mcr p15, 0, r0, c6, c6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mcr p15, 0, r0, c6, c7, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mcr p15, 0, r0, c6, c4, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mcr p15, 0, r0, c6, c5, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mcr p15, 0, r0, c6, c6, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mcr p15, 0, r0, c6, c7, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mov r0, #0x0000003F @ base = 0, size = 4GB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mcr p15, 0, r0, c6, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ldr r7, =CONFIG_DRAM_SIZE >> 12 @ size of RAM (must be >= 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pr_val r3, r0, r7, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mcr p15, 0, r3, c6, c1, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pr_val r3, r0, r6, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mcr p15, 0, r3, c6, c2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mov r0, #0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mcr p15, 0, r0, c2, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mov r0, #0x00 @ disable whole write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mov r0, #0x02 @ Region 1 write bufferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mcr p15, 0, r0, c3, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mov r0, #0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) sub r0, r0, #1 @ r0 = 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mcr p15, 0, r0, c5, c0, 0 @ all read/write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mcr p15, 0, r0, c5, c0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mrc p15, 0, r0, c1, c0 @ get control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) orr r0, r0, #0x00001000 @ I-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) orr r0, r0, #0x00000005 @ MPU/D-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .size __arm940_setup, . - __arm940_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) define_processor_functions arm940, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) string cpu_arch_name, "armv4t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) string cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) string cpu_arm940_name, "ARM940T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .type __arm940_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __arm940_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .long 0x41009400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .long 0xff00fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) initfn __arm940_setup, __arm940_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .long cpu_arm940_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .long arm940_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .long arm940_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .size __arm940_proc_info, . - __arm940_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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