^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999,2000 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * hacked for non-paged-MM by Hyok S. Choi, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * functions on the arm922.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * The size of one data cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CACHE_DLINESIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * The number of data cache segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CACHE_DSEGMENTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * The number of lines in a cache segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CACHE_DENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * This is the size at which it becomes more efficient to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * clean the whole cache, rather than using the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * cache line maintenance instructions. (I think this should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * be 32768).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CACHE_DLIMIT 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * cpu_arm922_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ENTRY(cpu_arm922_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * cpu_arm922_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ENTRY(cpu_arm922_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mrc p15, 0, r0, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bic r0, r0, #0x1000 @ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bic r0, r0, #0x000e @ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * cpu_arm922_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Perform a soft reset of the system. Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ENTRY(cpu_arm922_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mrc p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bic ip, ip, #0x000f @ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bic ip, ip, #0x1100 @ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mcr p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ENDPROC(cpu_arm922_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * cpu_arm922_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ENTRY(cpu_arm922_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ENTRY(arm922_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ENDPROC(arm922_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Clean and invalidate all cache entries in a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ENTRY(arm922_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ENTRY(arm922_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mov r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __flush_whole_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) subs r1, r1, #1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Clean and invalidate a range of cache entries in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * specified address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * - start - start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * - end - end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * - flags - vm_flags describing address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ENTRY(arm922_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sub r3, r1, r0 @ calculate total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cmp r3, #CACHE_DLIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bhs __flush_whole_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * region described by start, end. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ENTRY(arm922_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * region described by start, end. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ENTRY(arm922_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * - addr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * - size - region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ENTRY(arm922_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) add r1, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Invalidate (discard) the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * May not write back any entries. If 'start' or 'end'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * are not cache line aligned, those lines must be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) arm922_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tst r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tst r1, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Clean the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) arm922_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Clean and invalidate the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ENTRY(arm922_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ENTRY(arm922_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) add r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cmp r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) beq arm922_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bcs arm922_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) b arm922_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ENDPROC(arm922_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ENTRY(arm922_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ENDPROC(arm922_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .globl arm922_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .equ arm922_flush_kern_cache_louis, arm922_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) define_cache_functions arm922
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ENTRY(cpu_arm922_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) subs r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bhi 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * cpu_arm922_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ENTRY(cpu_arm922_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) @ && 'Clean & Invalidate whole DCache'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) @ && Re-written to use Index Ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) @ && Uses registers r1, r3 and ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) subs r1, r1, #1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * cpu_arm922_set_pte_ext(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ENTRY(cpu_arm922_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) armv3_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .type __arm922_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __arm922_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) adr r5, arm922_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ldmia r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mrc p15, 0, r0, c1, c0 @ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) bic r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) orr r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .size __arm922_setup, . - __arm922_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * ..11 0001 ..11 0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .type arm922_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) arm922_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) define_processor_functions arm922, dabort=v4t_early_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) string cpu_arch_name, "armv4t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) string cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) string cpu_arm922_name, "ARM922T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .type __arm922_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) __arm922_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .long 0x41009220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .long 0xff00fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) initfn __arm922_setup, __arm922_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .long cpu_arm922_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .long arm922_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .long v4wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .long v4wb_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .long arm922_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .long v4wt_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .size __arm922_proc_info, . - __arm922_proc_info
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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