^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999,2000 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * hacked for non-paged-MM by Hyok S. Choi, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * functions on the arm920.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The size of one data cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CACHE_DLINESIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The number of data cache segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CACHE_DSEGMENTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The number of lines in a cache segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CACHE_DENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * This is the size at which it becomes more efficient to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * clean the whole cache, rather than using the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * cache line maintenance instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CACHE_DLIMIT 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * cpu_arm920_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ENTRY(cpu_arm920_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * cpu_arm920_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ENTRY(cpu_arm920_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mrc p15, 0, r0, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bic r0, r0, #0x1000 @ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bic r0, r0, #0x000e @ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * cpu_arm920_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Perform a soft reset of the system. Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ENTRY(cpu_arm920_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mrc p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bic ip, ip, #0x000f @ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bic ip, ip, #0x1100 @ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mcr p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ret r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ENDPROC(cpu_arm920_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * cpu_arm920_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ENTRY(cpu_arm920_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ENTRY(arm920_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ENDPROC(arm920_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Invalidate all cache entries in a particular address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ENTRY(arm920_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ENTRY(arm920_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mov r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __flush_whole_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) subs r1, r1, #1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Invalidate a range of cache entries in the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * - start - start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * - end - end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * - flags - vm_flags for address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ENTRY(arm920_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sub r3, r1, r0 @ calculate total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cmp r3, #CACHE_DLIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bhs __flush_whole_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * region described by start, end. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ENTRY(arm920_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * region described by start, end. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ENTRY(arm920_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * - addr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * - size - region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ENTRY(arm920_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) add r1, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Invalidate (discard) the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * May not write back any entries. If 'start' or 'end'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * are not cache line aligned, those lines must be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) arm920_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tst r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tst r1, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Clean the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) arm920_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Clean and invalidate the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ENTRY(arm920_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ENTRY(arm920_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) add r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cmp r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) beq arm920_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bcs arm920_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) b arm920_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ENDPROC(arm920_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ENTRY(arm920_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ENDPROC(arm920_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .globl arm920_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) define_cache_functions arm920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ENTRY(cpu_arm920_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) subs r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bhi 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * cpu_arm920_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ENTRY(cpu_arm920_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) @ && 'Clean & Invalidate whole DCache'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) @ && Re-written to use Index Ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) @ && Uses registers r1, r3 and ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) subs r1, r1, #1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bcs 1b @ segments 7 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * cpu_arm920_set_pte(ptep, pte, ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ENTRY(cpu_arm920_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) armv3_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .globl cpu_arm920_suspend_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .equ cpu_arm920_suspend_size, 4 * 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef CONFIG_ARM_CPU_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ENTRY(cpu_arm920_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) stmfd sp!, {r4 - r6, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mrc p15, 0, r4, c13, c0, 0 @ PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) mrc p15, 0, r5, c3, c0, 0 @ Domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mrc p15, 0, r6, c1, c0, 0 @ Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) stmia r0, {r4 - r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ldmfd sp!, {r4 - r6, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ENDPROC(cpu_arm920_do_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ENTRY(cpu_arm920_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ldmia r0, {r4 - r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mcr p15, 0, r4, c13, c0, 0 @ PID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mcr p15, 0, r5, c3, c0, 0 @ Domain ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mcr p15, 0, r1, c2, c0, 0 @ TTB address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mov r0, r6 @ control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) b cpu_resume_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ENDPROC(cpu_arm920_do_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .type __arm920_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __arm920_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) adr r5, arm920_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ldmia r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mrc p15, 0, r0, c1, c0 @ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) bic r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) orr r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .size __arm920_setup, . - __arm920_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * ..11 0001 ..11 0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .type arm920_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) arm920_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) string cpu_arch_name, "armv4t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) string cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) string cpu_arm920_name, "ARM920T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .type __arm920_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __arm920_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .long 0x41009200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .long 0xff00fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) initfn __arm920_setup, __arm920_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .long cpu_arm920_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .long arm920_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .long v4wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .long v4wb_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .long arm920_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .long v4wt_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .size __arm920_proc_info, . - __arm920_proc_info
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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