^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/arm740.S: utility functions for ARM740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * cpu_arm740_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * cpu_arm740_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * cpu_arm740_dcache_clean_area()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * cpu_arm740_switch_mm()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * These are not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ENTRY(cpu_arm740_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ENTRY(cpu_arm740_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ENTRY(cpu_arm740_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ENTRY(cpu_arm740_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * cpu_arm740_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ENTRY(cpu_arm740_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) mrc p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bic r0, r0, #0x3f000000 @ bank/f/lock/s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bic r0, r0, #0x0000000c @ w-buffer/cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * cpu_arm740_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Params : r0 = address to jump to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Notes : This sets up everything for a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ENTRY(cpu_arm740_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bic ip, ip, #0x0000000c @ ............wc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mcr p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ENDPROC(cpu_arm740_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .type __arm740_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __arm740_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mcr p15, 0, r0, c6, c3 @ disable area 3~7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) mcr p15, 0, r0, c6, c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mcr p15, 0, r0, c6, c5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mcr p15, 0, r0, c6, c6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mcr p15, 0, r0, c6, c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mov r0, #0x0000003F @ base = 0, size = 4GB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mcr p15, 0, r0, c6, c0 @ set area 0, default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mov r4, #10 @ 11 is the minimum (4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 1: add r4, r4, #1 @ area size *= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) movs r3, r3, lsr #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bne 1b @ count not zero r-shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) orr r0, r0, r4, lsl #1 @ the area register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) orr r0, r0, #1 @ set enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mcr p15, 0, r0, c6, c1 @ set area 1, RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cmp r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) moveq r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) beq 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mov r4, #10 @ 11 is the minimum (4KB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 1: add r4, r4, #1 @ area size *= 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) movs r3, r3, lsr #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bne 1b @ count not zero r-shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) orr r0, r0, r4, lsl #1 @ the area register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) orr r0, r0, #1 @ set enable bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mov r0, #0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mov r0, #0x00 @ disable whole write buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mov r0, #0x02 @ Region 1 write bufferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mcr p15, 0, r0, c3, c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mov r0, #0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sub r0, r0, #1 @ r0 = 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mcr p15, 0, r0, c5, c0 @ all read/write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mrc p15, 0, r0, c1, c0 @ get control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bic r0, r0, #0x3F000000 @ set to standard caching mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) @ need some benchmark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) orr r0, r0, #0x0000000d @ MPU/Cache/WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .size __arm740_setup, . - __arm740_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) string cpu_arch_name, "armv4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) string cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) string cpu_arm740_name, "ARM740T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .type __arm740_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __arm740_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .long 0x41807400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .long 0xfffffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) initfn __arm740_setup, __arm740_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .long cpu_arm740_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .long arm740_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .long 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .long v4_cache_fns @ cache model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .size __arm740_proc_info, . - __arm740_proc_info
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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