Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *                     Rob Scott (rscott@mtrob.fdns.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  hacked for non-paged-MM by Hyok S. Choi, 2004.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * functions on the ARM720T.  The ARM720T has a writethrough IDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * cache, so we don't need to clean it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  Changelog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *   05-09-2000 SJH	Created by moving 720 specific functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *			out of 'proc-arm6,7.S' per RMK discussion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   07-25-2000 SJH	Added idle function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *   08-25-2000	DBS	Updated for integration of ARM Ltd version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *   04-20-2004 HSC	modified for non-paged memory management mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * Function: arm720_proc_init (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *	   : arm720_proc_fin (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * Notes   : This processor does not require these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) ENTRY(cpu_arm720_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) ENTRY(cpu_arm720_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) ENTRY(cpu_arm720_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		mrc	p15, 0, r0, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		bic	r0, r0, #0x1000			@ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		bic	r0, r0, #0x000e			@ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Function: arm720_proc_do_idle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * Params  : r0 = unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * Purpose : put the processor in proper idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) ENTRY(cpu_arm720_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * Function: arm720_switch_mm(unsigned long pgd_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Params  : pgd_phys	Physical address of page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * Purpose : Perform a task switch, saving the old process' state and restoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	     the new.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) ENTRY(cpu_arm720_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		mov	r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		mcr	p15, 0, r1, c7, c7, 0		@ invalidate cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		mcr	p15, 0, r1, c8, c7, 0		@ flush TLB (v4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * Params  : r0 = Address to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *	   : r1 = value to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * Purpose : Set a PTE and flush it out of any WB cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) ENTRY(cpu_arm720_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	armv3_set_pte_ext wc_disable=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * Function: arm720_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * Params  : r0 = address to jump to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * Notes   : This sets up everything for a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) ENTRY(cpu_arm720_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		bic	ip, ip, #0x000f			@ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		bic	ip, ip, #0x2100			@ ..v....s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ENDPROC(cpu_arm720_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.type	__arm710_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __arm710_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mrc	p15, 0, r0, c1, c0		@ get control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ldr	r5, arm710_cr1_clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ldr	r5, arm710_cr1_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	orr	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ret	lr				@ __ret (head.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.size	__arm710_setup, . - __arm710_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 *  R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * .... 0001 ..11 1101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.type	arm710_cr1_clear, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.type	arm710_cr1_set, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) arm710_cr1_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.word	0x0f3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) arm710_cr1_set:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.word	0x013d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.type	__arm720_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __arm720_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	adr	r5, arm720_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ldmia	r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mrc	p15, 0, r0, c1, c0		@ get control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	orr	r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret	lr				@ __ret (head.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.size	__arm720_setup, . - __arm720_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 *  R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * ..1. 1001 ..11 1101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.type	arm720_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) arm720_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	crval	clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	string	cpu_arch_name, "armv4t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	string	cpu_elf_name, "v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	string	cpu_arm710_name, "ARM710T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	string	cpu_arm720_name, "ARM720T"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * See <asm/procinfo.h> for a definition of this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.type	__\name\()_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __\name\()_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.long	\cpu_val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.long	\cpu_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			PMD_SECT_BUFFERABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			PMD_SECT_CACHEABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		initfn	\cpu_flush, __\name\()_proc_info	@ cpu_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.long	cpu_arch_name				@ arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.long	cpu_elf_name				@ elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB	@ elf_hwcap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.long	\cpu_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.long	arm720_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.long	v4_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.long	v4wt_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.long	v4_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.size	__\name\()_proc_info, . - __\name\()_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup