Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2000 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * functions on the arm1020e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * This is the maximum size of an area which will be invalidated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * using the single invalidate entry instructions.  Anything larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * than this, and we go for the whole cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * This value should be chosen such that we choose the cheapest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * alternative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX_AREA_SIZE	32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * The size of one data cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CACHE_DLINESIZE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * The number of data cache segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CACHE_DSEGMENTS	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * The number of lines in a cache segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CACHE_DENTRIES	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * This is the size at which it becomes more efficient to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * clean the whole cache, rather than using the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * cache line maintenance instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CACHE_DLIMIT	32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * cpu_arm1020e_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) ENTRY(cpu_arm1020e_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * cpu_arm1020e_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) ENTRY(cpu_arm1020e_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	bic	r0, r0, #0x1000 		@ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	bic	r0, r0, #0x000e 		@ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * cpu_arm1020e_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * Perform a soft reset of the system.	Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) ENTRY(cpu_arm1020e_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	bic	ip, ip, #0x000f 		@ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	bic	ip, ip, #0x1100 		@ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ret	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) ENDPROC(cpu_arm1020e_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * cpu_arm1020e_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ENTRY(cpu_arm1020e_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* ================================= CACHE ================================ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  *	flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *	Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ENTRY(arm1020e_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ENDPROC(arm1020e_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *	flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	Invalidate all cache entries in a particular address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *	space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ENTRY(arm1020e_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *	flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  *	Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ENTRY(arm1020e_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mov	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __flush_whole_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	subs	r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	bcs	2b				@ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	subs	r1, r1, #1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	bcs	1b				@ segments 15 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  *	flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  *	Invalidate a range of cache entries in the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *	address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *	- start	- start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	- end	- end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	- flags	- vm_flags for this space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ENTRY(arm1020e_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	sub	r3, r1, r0			@ calculate total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	cmp	r3, #CACHE_DLIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	bhs	__flush_whole_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	tst	r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *	coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *	Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  *	region described by start.  If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *	Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ENTRY(arm1020e_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *	coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *	Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  *	region described by start.  If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  *	Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ENTRY(arm1020e_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *	flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  *	Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  *	the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  *	- addr	- kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  *	- size	- region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ENTRY(arm1020e_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	add	r1, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *	dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  *	Invalidate (discard) the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  *	May not write back any entries.  If 'start' or 'end'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *	are not cache line aligned, those lines must be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *	back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) arm1020e_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	tst	r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	tst	r1, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  *	dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  *	Clean the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) arm1020e_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  *	dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  *	Clean and invalidate the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  *	- start	- virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *	- end	- virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ENTRY(arm1020e_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	bic	r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	cmp	r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	blo	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  *	dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  *	- start	- kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  *	- size	- size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  *	- dir	- DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ENTRY(arm1020e_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	add	r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	cmp	r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	beq	arm1020e_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	bcs	arm1020e_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	b	arm1020e_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ENDPROC(arm1020e_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  *	dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  *	- start	- kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  *	- size	- size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  *	- dir	- DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ENTRY(arm1020e_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ENDPROC(arm1020e_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.globl	arm1020e_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.equ	arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	define_cache_functions arm1020e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ENTRY(cpu_arm1020e_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	add	r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	subs	r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	bhi	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * cpu_arm1020e_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ENTRY(cpu_arm1020e_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	mcr	p15, 0, r3, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	mov	r1, #0xF			@ 16 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 1:	mov	r3, #0x3F			@ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 2:	mov	ip, r3, LSL #26 		@ shift up entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	orr	ip, ip, r1, LSL #5		@ shift in/up index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	mov	ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	subs	r3, r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	cmp	r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	bge	2b				@ entries 3F to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	subs	r1, r1, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	cmp	r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	bge	1b				@ segments 15 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	mov	r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)         
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)  * cpu_arm1020e_set_pte(ptep, pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ENTRY(cpu_arm1020e_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	armv3_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	mov	r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.type	__arm1020e_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __arm1020e_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	mov	r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	adr	r5, arm1020e_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	ldmia	r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	mrc	p15, 0, r0, c1, c0		@ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	bic	r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	orr	r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.size	__arm1020e_setup, . - __arm1020e_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	 *  R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	 * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	 * .011 1001 ..11 0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.type	arm1020e_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) arm1020e_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	__INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	string	cpu_arch_name, "armv5te"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	string	cpu_elf_name, "v5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	string	cpu_arm1020e_name, "ARM1020E"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.type	__arm1020e_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __arm1020e_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.long	0x4105a200			@ ARM 1020TE (Architecture v5TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.long	0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.long   PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		PMD_BIT4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	initfn	__arm1020e_setup, __arm1020e_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	.long	cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	.long	cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.long	cpu_arm1020e_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.long	arm1020e_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.long	v4wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.long	v4wb_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.long	arm1020e_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	.size	__arm1020e_proc_info, . - __arm1020e_proc_info