^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * hacked for non-paged-MM by Hyok S. Choi, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * These are the low level assembler for performing cache and TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * functions on the arm1020.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/hwcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/pgtable-hwdef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "proc-macros.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This is the maximum size of an area which will be invalidated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * using the single invalidate entry instructions. Anything larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * than this, and we go for the whole cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * This value should be chosen such that we choose the cheapest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * alternative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX_AREA_SIZE 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The size of one data cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CACHE_DLINESIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The number of data cache segments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CACHE_DSEGMENTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The number of lines in a cache segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CACHE_DENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * This is the size at which it becomes more efficient to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * clean the whole cache, rather than using the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * cache line maintenance instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CACHE_DLIMIT 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * cpu_arm1020_proc_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ENTRY(cpu_arm1020_proc_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * cpu_arm1020_proc_fin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ENTRY(cpu_arm1020_proc_fin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mrc p15, 0, r0, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bic r0, r0, #0x1000 @ ...i............
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bic r0, r0, #0x000e @ ............wca.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mcr p15, 0, r0, c1, c0, 0 @ disable caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * cpu_arm1020_reset(loc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Perform a soft reset of the system. Put the CPU into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * same state as it would be if it had been reset, and branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * to what would be the reset vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * loc: location to jump to for soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .pushsection .idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ENTRY(cpu_arm1020_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mrc p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bic ip, ip, #0x000f @ ............wcam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bic ip, ip, #0x1100 @ ...i...s........
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mcr p15, 0, ip, c1, c0, 0 @ ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ENDPROC(cpu_arm1020_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * cpu_arm1020_do_idle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ENTRY(cpu_arm1020_do_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* ================================= CACHE ================================ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * flush_icache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Unconditionally clean and invalidate the entire icache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ENTRY(arm1020_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ENDPROC(arm1020_flush_icache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * flush_user_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Invalidate all cache entries in a particular address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ENTRY(arm1020_flush_user_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * flush_kern_cache_all()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Clean and invalidate the entire cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ENTRY(arm1020_flush_kern_cache_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mov r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __flush_whole_cache:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) subs r3, r3, #1 << 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bcs 2b @ entries 63 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) subs r1, r1, #1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bcs 1b @ segments 15 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * flush_user_cache_range(start, end, flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Invalidate a range of cache entries in the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * - start - start address (inclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * - end - end address (exclusive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * - flags - vm_flags for this space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ENTRY(arm1020_flush_user_cache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sub r3, r1, r0 @ calculate total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cmp r3, #CACHE_DLIMIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bhs __flush_whole_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mcr p15, 0, ip, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tst r2, #VM_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * coherent_kern_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * region described by start. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ENTRY(arm1020_coherent_kern_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* FALLTRHOUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * coherent_user_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Ensure coherency between the Icache and the Dcache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * region described by start. If you have non-snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Harvard caches, you need to implement this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ENTRY(arm1020_coherent_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mcr p15, 0, ip, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * flush_kern_dcache_area(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Ensure no D cache aliasing occurs, either with itself or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * the I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * - addr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * - size - region size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ENTRY(arm1020_flush_kern_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) add r1, r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * dma_inv_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Invalidate (discard) the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * May not write back any entries. If 'start' or 'end'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * are not cache line aligned, those lines must be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) arm1020_dma_inv_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tst r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mcrne p15, 0, ip, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tst r1, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mcrne p15, 0, ip, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mcrne p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * dma_clean_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Clean the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * (same as v4wb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) arm1020_dma_clean_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * dma_flush_range(start, end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Clean and invalidate the specified virtual address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * - start - virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * - end - virtual end address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ENTRY(arm1020_dma_flush_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) bic r0, r0, #CACHE_DLINESIZE - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mcr p15, 0, ip, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cmp r0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) blo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ENTRY(arm1020_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) add r1, r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cmp r2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) beq arm1020_dma_clean_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bcs arm1020_dma_inv_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) b arm1020_dma_flush_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ENDPROC(arm1020_dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ENTRY(arm1020_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ENDPROC(arm1020_dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .globl arm1020_flush_kern_cache_louis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) define_cache_functions arm1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ENTRY(cpu_arm1020_dcache_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mcr p15, 0, ip, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) add r0, r0, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) subs r1, r1, #CACHE_DLINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bhi 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* =============================== PageTable ============================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * cpu_arm1020_switch_mm(pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Set the translation base pointer to be as described by pgd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * pgd: new page tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ENTRY(cpu_arm1020_switch_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mcr p15, 0, r3, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mov r1, #0xF @ 16 segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 1: mov r3, #0x3F @ 64 entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 2: mov ip, r3, LSL #26 @ shift up entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) orr ip, ip, r1, LSL #5 @ shift in/up index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mov ip, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mcr p15, 0, ip, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) subs r3, r3, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cmp r3, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bge 2b @ entries 3F to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) subs r1, r1, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cmp r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bge 1b @ segments 15 to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mov r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mcr p15, 0, r1, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * cpu_arm1020_set_pte(ptep, pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Set a PTE and flush it out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ENTRY(cpu_arm1020_set_pte_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) armv3_set_pte_ext
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mov r0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mcr p15, 0, r0, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mcr p15, 0, r0, c7, c10, 1 @ clean D entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mcr p15, 0, r0, c7, c10, 4 @ drain WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .type __arm1020_setup, #function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __arm1020_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mov r0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) adr r5, arm1020_crval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ldmia r5, {r5, r6}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mrc p15, 0, r0, c1, c0 @ get control register v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bic r0, r0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) orr r0, r0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) orr r0, r0, #0x4000 @ .R.. .... .... ....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .size __arm1020_setup, . - __arm1020_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * .RVI ZFRS BLDP WCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * .011 1001 ..11 0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .type arm1020_crval, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) arm1020_crval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __INITDATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .section ".rodata"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) string cpu_arch_name, "armv5t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) string cpu_elf_name, "v5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .type cpu_arm1020_name, #object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) cpu_arm1020_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .ascii "ARM1020"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #ifndef CONFIG_CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ascii "i"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #ifndef CONFIG_CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .ascii "d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .ascii "(wt)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ascii "(wb)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #ifndef CONFIG_CPU_BPREDICT_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .ascii "B"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .ascii "RR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .ascii "\0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .size cpu_arm1020_name, . - cpu_arm1020_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .section ".proc.info.init", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .type __arm1020_proc_info,#object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __arm1020_proc_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .long 0x4104a200 @ ARM 1020T (Architecture v5T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .long 0xff0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .long PMD_TYPE_SECT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PMD_SECT_AP_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PMD_SECT_AP_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) initfn __arm1020_setup, __arm1020_proc_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .long cpu_arch_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .long cpu_elf_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .long cpu_arm1020_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .long arm1020_processor_functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .long v4wbi_tlb_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .long v4wb_user_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .long arm1020_cache_fns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .size __arm1020_proc_info, . - __arm1020_proc_info
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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