Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Based on linux/arch/arm/mm/nommu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * ARM PMSAv7 supporting functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/mpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "mm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	phys_addr_t base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	phys_addr_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	unsigned long subreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static struct region __initdata mem[MPU_MAX_REGIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static struct region __initdata xip[MPU_MAX_REGIONS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static unsigned int __initdata mpu_min_region_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static unsigned int __initdata mpu_max_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static int __init __mpu_min_region_order(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static int __init __mpu_max_regions(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #ifndef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DRBAR	__ACCESS_CP15(c6, 0, c1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IRBAR	__ACCESS_CP15(c6, 0, c1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DRSR	__ACCESS_CP15(c6, 0, c1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IRSR	__ACCESS_CP15(c6, 0, c1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DRACR	__ACCESS_CP15(c6, 0, c1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IRACR	__ACCESS_CP15(c6, 0, c1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RNGNR	__ACCESS_CP15(c6, 0, c2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Region number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static inline void rgnr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	write_sysreg(v, RNGNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* Data-side / unified region attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Region access control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static inline void dracr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	write_sysreg(v, DRACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Region size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static inline void drsr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	write_sysreg(v, DRSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Region base address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline void drbar_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	write_sysreg(v, DRBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static inline u32 drbar_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return read_sysreg(DRBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Optional instruction-side region attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* I-side Region access control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static inline void iracr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	write_sysreg(v, IRACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* I-side Region size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static inline void irsr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	write_sysreg(v, IRSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* I-side Region base address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static inline void irbar_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	write_sysreg(v, IRBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static inline u32 irbar_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return read_sysreg(IRBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void rgnr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Data-side / unified region attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Region access control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void dracr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Region size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline void drsr_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Region base address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void drbar_write(u32 v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline u32 drbar_read(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* ARMv7-M only supports a unified MPU, so I-side operations are nop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void iracr_write(u32 v) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline void irsr_write(u32 v) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline void irbar_write(u32 v) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline unsigned long irbar_read(void) {return 0;}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned long  subreg, bslots, sslots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	phys_addr_t abase = base & ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	phys_addr_t asize = base + size - abase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	phys_addr_t p2size = 1 << __fls(asize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	phys_addr_t bdiff, sdiff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (p2size != asize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		p2size *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	bdiff = base - abase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	sdiff = p2size - asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	subreg = p2size / PMSAv7_NR_SUBREGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if ((bdiff % subreg) || (sdiff % subreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	bslots = bdiff / subreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	sslots = sdiff / subreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (bslots || sslots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (subreg < PMSAv7_MIN_SUBREG_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		if (bslots + sslots > PMSAv7_NR_SUBREGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		for (i = 0; i < bslots; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			_set_bit(i, &region->subreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		for (i = 1; i <= sslots; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			_set_bit(PMSAv7_NR_SUBREGS - i, &region->subreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	region->base = abase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	region->size = p2size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init allocate_region(phys_addr_t base, phys_addr_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				  unsigned int limit, struct region *regions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	phys_addr_t diff = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int attempts = MPU_MAX_REGIONS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	while (diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		/* Try cover region as is (maybe with help of subregions) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (try_split_region(base, size, &regions[count])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			base += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			diff -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			size = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			 * Maximum aligned region might overflow phys_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			 * if "base" is 0. Hence we keep everything below 4G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			 * until we take the smaller of the aligned region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			 * size ("asize") and rounded region size ("p2size"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			 * one of which is guaranteed to be smaller than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			 * maximum physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			phys_addr_t asize = (base - 1) ^ base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			phys_addr_t p2size = (1 <<  __fls(diff)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			size = asize < p2size ? asize + 1 : p2size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (count > limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (!attempts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		attempts--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* MPU initialisation functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void __init pmsav7_adjust_lowmem_bounds(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	phys_addr_t  specified_mem_size = 0, total_mem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	phys_addr_t mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	phys_addr_t mem_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	phys_addr_t reg_start, reg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	unsigned int mem_max_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	bool first = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u64 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Free-up PMSAv7_PROBE_REGION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mpu_min_region_order = __mpu_min_region_order();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* How many regions are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	mpu_max_regions = __mpu_max_regions();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mem_max_regions = min((unsigned int)MPU_MAX_REGIONS, mpu_max_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* We need to keep one slot for background region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mem_max_regions--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #ifndef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/* ... and one for vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mem_max_regions--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* plus some regions to cover XIP ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	num = allocate_region(CONFIG_XIP_PHYS_ADDR, __pa(_exiprom) - CONFIG_XIP_PHYS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			      mem_max_regions, xip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	mem_max_regions -= num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	for_each_mem_range(i, &reg_start, &reg_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			phys_addr_t phys_offset = PHYS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			 * Initially only use memory continuous from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			 * PHYS_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			if (reg_start != phys_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				panic("First memory bank must be contiguous from PHYS_OFFSET");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			mem_start = reg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			mem_end = reg_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			specified_mem_size = mem_end - mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			first = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			 * memblock auto merges contiguous blocks, remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			 * all blocks afterwards in one go (we can't remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			 * blocks separately while iterating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				  &mem_end, &reg_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			memblock_remove(reg_start, 0 - reg_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	memset(mem, 0, sizeof(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	num = allocate_region(mem_start, specified_mem_size, mem_max_regions, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		unsigned long  subreg = mem[i].size / PMSAv7_NR_SUBREGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		total_mem_size += mem[i].size - subreg * hweight_long(mem[i].subreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		pr_debug("MPU: base %pa size %pa disable subregions: %*pbl\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			 &mem[i].base, &mem[i].size, PMSAv7_NR_SUBREGS, &mem[i].subreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (total_mem_size != specified_mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				&specified_mem_size, &total_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		memblock_remove(mem_start + total_mem_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				specified_mem_size - total_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int __init __mpu_max_regions(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	 * We don't support a different number of I/D side regions so if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	 * have separate instruction and data memory maps then return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	 * whichever side has a smaller number of supported regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	u32 dregions, iregions, mpuir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mpuir = read_cpuid_mputype();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* Check for separate d-side and i-side memory maps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (mpuir & MPUIR_nU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* Use the smallest of the two maxima */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return min(dregions, iregions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int __init mpu_iside_independent(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* MPUIR.nU specifies whether there is *not* a unified memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return read_cpuid_mputype() & MPUIR_nU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int __init __mpu_min_region_order(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u32 drbar_result, irbar_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	/* We've kept a region free for this probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	rgnr_write(PMSAv7_PROBE_REGION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	 * region order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	drbar_write(0xFFFFFFFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	drbar_result = irbar_result = drbar_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	drbar_write(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	/* If the MPU is non-unified, we use the larger of the two minima*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (mpu_iside_independent()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		irbar_write(0xFFFFFFFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		irbar_result = irbar_read();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		irbar_write(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	isb(); /* Ensure that MPU region operations have completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* Return whichever result is larger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return __ffs(max(drbar_result, irbar_result));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int __init mpu_setup_region(unsigned int number, phys_addr_t start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				   unsigned int size_order, unsigned int properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				   unsigned int subregions, bool need_flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	u32 size_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* We kept a region free for probing resolution of MPU regions*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (number > mpu_max_regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	    || number >= MPU_MAX_REGIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (size_order > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (size_order < mpu_min_region_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	/* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	size_data = ((size_order - 1) << PMSAv7_RSR_SZ) | 1 << PMSAv7_RSR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	size_data |= subregions << PMSAv7_RSR_SD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (need_flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	dsb(); /* Ensure all previous data accesses occur with old mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	rgnr_write(number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	drbar_write(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dracr_write(properties);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	isb(); /* Propagate properties before enabling region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	drsr_write(size_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/* Check for independent I-side registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (mpu_iside_independent()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		irbar_write(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		iracr_write(properties);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		irsr_write(size_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	isb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	/* Store region info (we treat i/d side the same, so only store d) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	mpu_rgn_info.rgns[number].dracr = properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	mpu_rgn_info.rgns[number].drbar = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	mpu_rgn_info.rgns[number].drsr = size_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	mpu_rgn_info.used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Set up default MPU regions, doing nothing if there is no MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __init pmsav7_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	int i, region = 0, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	/* Setup MPU (order is important) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* Background */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	err |= mpu_setup_region(region++, 0, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 				PMSAv7_ACR_XN | PMSAv7_RGN_STRONGLY_ORDERED | PMSAv7_AP_PL1RW_PL0RW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 				0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	/* ROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	for (i = 0; i < ARRAY_SIZE(xip); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)                  * In case we overwrite RAM region we set earlier in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)                  * head-nommu.S (which is cachable) all subsequent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)                  * data access till we setup RAM bellow would be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)                  * with BG region (which is uncachable), thus we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)                  * to clean and invalidate cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		bool need_flush = region == PMSAv7_RAM_REGION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		if (!xip[i].size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		err |= mpu_setup_region(region++, xip[i].base, ilog2(xip[i].size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 					PMSAv7_AP_PL1RO_PL0NA | PMSAv7_RGN_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 					xip[i].subreg, need_flush);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	/* RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	for (i = 0; i < ARRAY_SIZE(mem); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		if (!mem[i].size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		err |= mpu_setup_region(region++, mem[i].base, ilog2(mem[i].size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 					PMSAv7_AP_PL1RW_PL0RW | PMSAv7_RGN_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 					mem[i].subreg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	/* Vectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #ifndef CONFIG_CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	err |= mpu_setup_region(region++, vectors_base, ilog2(2 * PAGE_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 				PMSAv7_AP_PL1RW_PL0NA | PMSAv7_RGN_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 				0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		panic("MPU region initialization failure! %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		pr_info("Using ARMv7 PMSA Compliant MPU. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			 "Region independence: %s, Used %d of %d regions\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 			mpu_iside_independent() ? "Yes" : "No",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 			mpu_rgn_info.used, mpu_max_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }