^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mm/mmu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2005 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/nodemask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cachetype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/procinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/pgalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "fault.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "mm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "tcm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern unsigned long __atags_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * empty_zero_page is a special page that is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * zero-initialized data and COW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct page *empty_zero_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) EXPORT_SYMBOL(empty_zero_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * The pmd table for the upper-most set of pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pmd_t *top_pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pmdval_t user_pmd_table = _PAGE_USER_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CPOLICY_UNCACHED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CPOLICY_BUFFERED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CPOLICY_WRITETHROUGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CPOLICY_WRITEBACK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CPOLICY_WRITEALLOC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static unsigned int ecc_mask __initdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pgprot_t pgprot_user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pgprot_t pgprot_kernel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) EXPORT_SYMBOL(pgprot_user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EXPORT_SYMBOL(pgprot_kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct cachepolicy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const char policy[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int cr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pmdval_t pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pteval_t pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct cachepolicy cache_policies[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .policy = "uncached",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .cr_mask = CR_W|CR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .pmd = PMD_SECT_UNCACHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .pte = L_PTE_MT_UNCACHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .policy = "buffered",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .cr_mask = CR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .pmd = PMD_SECT_BUFFERED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .pte = L_PTE_MT_BUFFERABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .policy = "writethrough",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .cr_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .pmd = PMD_SECT_WT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .pte = L_PTE_MT_WRITETHROUGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .policy = "writeback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .cr_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .pmd = PMD_SECT_WB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pte = L_PTE_MT_WRITEBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .policy = "writealloc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .cr_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .pmd = PMD_SECT_WBWA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .pte = L_PTE_MT_WRITEALLOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #ifdef CONFIG_CPU_CP15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned long initial_pmd_value __initdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Initialise the cache_policy variable with the initial state specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * via the "pmd" value. This is used to ensure that on ARMv6 and later,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * the C code sets the page tables up with the same policy as the head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * assembly code, which avoids an illegal state where the TLBs can get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * confused. See comments in early_cachepolicy() for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __init init_default_cache_policy(unsigned long pmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) initial_pmd_value = pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pmd &= PMD_SECT_CACHE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (cache_policies[i].pmd == pmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cachepolicy = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (i == ARRAY_SIZE(cache_policies))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err("ERROR: could not find cache policy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * These are useful for identifying cache coherency problems by allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * the cache or the cache and writebuffer to be turned off. (Note: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * write buffer should not be on and the cache off).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int __init early_cachepolicy(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i, selected = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int len = strlen(cache_policies[i].policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (memcmp(p, cache_policies[i].policy, len) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) selected = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (selected == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_err("ERROR: unknown or unsupported cache policy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * This restriction is partly to do with the way we boot; it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * unpredictable to have memory mapped using two different sets of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * memory attributes (shared, type, and cache attribs). We can not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * change these attributes once the initial assembly has setup the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cache_policies[cachepolicy].policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (selected != cachepolicy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) cachepolicy = selected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) set_cr(cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) early_param("cachepolicy", early_cachepolicy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int __init early_nocache(char *__unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) char *p = "buffered";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) early_cachepolicy(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) early_param("nocache", early_nocache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int __init early_nowrite(char *__unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) char *p = "uncached";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) early_cachepolicy(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) early_param("nowb", early_nowrite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int __init early_ecc(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (memcmp(p, "on", 2) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ecc_mask = PMD_PROTECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else if (memcmp(p, "off", 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ecc_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) early_param("ecc", early_ecc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #else /* ifdef CONFIG_CPU_CP15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int __init early_cachepolicy(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_warn("cachepolicy kernel parameter not supported without cp15\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) early_param("cachepolicy", early_cachepolicy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int __init noalign_setup(char *__unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_warn("noalign kernel parameter not supported without cp15\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __setup("noalign", noalign_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif /* ifdef CONFIG_CPU_CP15 / else */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct mem_type mem_types[] __ro_after_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) L_PTE_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .domain = DOMAIN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .prot_sect = PROT_SECT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .domain = DOMAIN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [MT_DEVICE_CACHED] = { /* ioremap_cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .domain = DOMAIN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [MT_DEVICE_WC] = { /* ioremap_wc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .prot_sect = PROT_SECT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .domain = DOMAIN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [MT_UNCACHED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .prot_pte = PROT_PTE_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .domain = DOMAIN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [MT_CACHECLEAN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [MT_MINICLEAN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [MT_LOW_VECTORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) L_PTE_RDONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .domain = DOMAIN_VECTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [MT_HIGH_VECTORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) L_PTE_USER | L_PTE_RDONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .domain = DOMAIN_VECTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [MT_MEMORY_RWX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [MT_MEMORY_RW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) L_PTE_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [MT_ROM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .prot_sect = PMD_TYPE_SECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [MT_MEMORY_RWX_NONCACHED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) L_PTE_MT_BUFFERABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [MT_MEMORY_RW_DTCM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) L_PTE_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [MT_MEMORY_RWX_ITCM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [MT_MEMORY_RW_SO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) L_PTE_MT_UNCACHED | L_PTE_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PMD_SECT_UNCACHED | PMD_SECT_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [MT_MEMORY_DMA_READY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) L_PTE_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .prot_l1 = PMD_TYPE_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .domain = DOMAIN_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const struct mem_type *get_mem_type(unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXPORT_SYMBOL(get_mem_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return &bm_pte[pte_index(addr)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return pte_offset_kernel(dir, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline pmd_t * __init fixmap_pmd(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return pmd_off_k(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void __init early_fixmap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pmd_t *pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * The early fixmap range spans multiple pmds, for which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * we are not prepared:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) != FIXADDR_TOP >> PMD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pmd = fixmap_pmd(FIXADDR_TOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pmd_populate_kernel(&init_mm, pmd, bm_pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pte_offset_fixmap = pte_offset_early_fixmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * As a result, this can only be called with preemption disabled, as under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * stop_machine().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long vaddr = __fix_to_virt(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Make sure fixmap region does not exceed available allocation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FIXADDR_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BUG_ON(idx >= __end_of_fixed_addresses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* We support only device mappings before pgprot_kernel is set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (pgprot_val(prot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) set_pte_at(NULL, vaddr, pte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pfn_pte(phys >> PAGE_SHIFT, prot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pte_clear(NULL, vaddr, pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Adjust the PMD section entries according to the CPU in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void __init build_mem_type_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct cachepolicy *cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int cr = get_cr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int cpu_arch = cpu_architecture();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (cpu_arch < CPU_ARCH_ARMv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #if defined(CONFIG_CPU_DCACHE_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (cachepolicy > CPOLICY_BUFFERED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cachepolicy = CPOLICY_BUFFERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (cachepolicy > CPOLICY_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cachepolicy = CPOLICY_WRITETHROUGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (cpu_arch < CPU_ARCH_ARMv5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (cachepolicy >= CPOLICY_WRITEALLOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cachepolicy = CPOLICY_WRITEBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ecc_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (is_smp()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (cachepolicy != CPOLICY_WRITEALLOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pr_warn("Forcing write-allocate cache policy for SMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cachepolicy = CPOLICY_WRITEALLOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!(initial_pmd_value & PMD_SECT_S)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pr_warn("Forcing shared mappings for SMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) initial_pmd_value |= PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Strip out features not present on earlier architectures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * without extended page tables don't have the 'Shared' bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (cpu_arch < CPU_ARCH_ARMv5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) for (i = 0; i < ARRAY_SIZE(mem_types); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < ARRAY_SIZE(mem_types); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mem_types[i].prot_sect &= ~PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * ARMv5 and lower, bit 4 must be set for page tables (was: cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * "update-able on write" bit on ARM610). However, Xscale and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Xscale3 require this bit to be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (cpu_is_xscale_family()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mem_types[i].prot_sect &= ~PMD_BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mem_types[i].prot_l1 &= ~PMD_BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } else if (cpu_arch < CPU_ARCH_ARMv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (mem_types[i].prot_l1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mem_types[i].prot_l1 |= PMD_BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (mem_types[i].prot_sect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mem_types[i].prot_sect |= PMD_BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Mark the device areas according to the CPU/architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!cpu_is_xsc3()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Mark device regions on ARMv6+ as execute-never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * to prevent speculative instruction fetches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Also setup NX memory mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * For ARMv7 with TEX remapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * - shared device is SXCB=1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * - nonshared device is SXCB=0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * - write combine device mem is SXCB=0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * (Uncached Normal memory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else if (cpu_is_xsc3()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * For Xscale3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * - shared device is TEXCB=00101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * - nonshared device is TEXCB=01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * - write combine device mem is TEXCB=00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * (Inner/Outer Uncacheable in xsc3 parlance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * For ARMv6 and ARMv7 without TEX remapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * - shared device is TEXCB=00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * - nonshared device is TEXCB=01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * - write combine device mem is TEXCB=00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * (Uncached Normal in ARMv6 parlance).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * On others, write combining is "Uncached/Buffered"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Now deal with the memory-type mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) cp = &cache_policies[cachepolicy];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * We don't use domains on ARMv6 (since this causes problems with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * v6/v7 kernels), so we must use a separate memory type for user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * r/o, kernel r/w to map the vectors page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (cpu_arch == CPU_ARCH_ARMv6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) vecs_pgprot |= L_PTE_MT_VECTORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Check is it with support for the PXN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * in the Short-descriptor translation table format descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (cpu_arch == CPU_ARCH_ARMv7 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) user_pmd_table |= PMD_PXNTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * ARMv6 and above have extended page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Mark cache clean areas and XIP ROM read only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * from SVC mode and no access from userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * If the initial page tables were created with the S bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * set, then we need to do the same here for the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * reasons given in early_cachepolicy().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (initial_pmd_value & PMD_SECT_S) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) user_pgprot |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) kern_pgprot |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) vecs_pgprot |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Non-cacheable Normal - intended for memory areas that must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * not cause dirty cache line writebacks when used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (cpu_arch >= CPU_ARCH_ARMv6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Non-cacheable Normal is XCB = 001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PMD_SECT_BUFFERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* For both ARMv6 and non-TEX-remapping ARMv7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PMD_SECT_TEX(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Do not generate access flag faults for the kernel mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mem_types[i].prot_pte |= PTE_EXT_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (mem_types[i].prot_sect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mem_types[i].prot_sect |= PMD_SECT_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) kern_pgprot |= PTE_EXT_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) vecs_pgprot |= PTE_EXT_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Set PXN for user mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) user_pgprot |= PTE_EXT_PXN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pteval_t v = pgprot_val(protection_map[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) protection_map[i] = __pgprot(v | user_pgprot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) L_PTE_DIRTY | kern_pgprot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mem_types[MT_ROM].prot_sect |= cp->pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) switch (cp->pmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case PMD_SECT_WT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case PMD_SECT_WB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case PMD_SECT_WBWA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pr_info("Memory policy: %sData cache %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ecc_mask ? "ECC enabled, " : "", cp->policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct mem_type *t = &mem_types[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (t->prot_l1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) t->prot_l1 |= PMD_DOMAIN(t->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (t->prot_sect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) t->prot_sect |= PMD_DOMAIN(t->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned long size, pgprot_t vma_prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!pfn_valid(pfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return pgprot_noncached(vma_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else if (file->f_flags & O_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return pgprot_writecombine(vma_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return vma_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) EXPORT_SYMBOL(phys_mem_access_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void __init *early_alloc(unsigned long sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void *ptr = memblock_alloc(sz, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) __func__, sz, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void *__init late_alloc(unsigned long sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned long prot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void *(*alloc)(unsigned long sz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (pmd_none(*pmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __pmd_populate(pmd, __pa(pte), prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) BUG_ON(pmd_bad(*pmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return pte_offset_kernel(pmd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned long prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return arm_pte_alloc(pmd, addr, prot, early_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned long end, unsigned long pfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) const struct mem_type *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void *(*alloc)(unsigned long sz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ng ? PTE_EXT_NG : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pfn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } while (pte++, addr += PAGE_SIZE, addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unsigned long end, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) const struct mem_type *type, bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) pmd_t *p = pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * In classic MMU format, puds and pmds are folded in to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * group of L1 entries making up one logical pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * an L2 table (2MB), where as PMDs refer to the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * L1 entries (1MB). Hence increment to get the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * offset for odd 1MB sections.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * (See arch/arm/include/asm/pgtable-2level.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (addr & SECTION_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pmd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) phys += SECTION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } while (pmd++, addr += SECTION_SIZE, addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) flush_pmd_entry(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) unsigned long end, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) const struct mem_type *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void *(*alloc)(unsigned long sz), bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pmd_t *pmd = pmd_offset(pud, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned long next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * With LPAE, we must loop over to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * all the pmds for the given range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) next = pmd_addr_end(addr, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Try a section mapping - addr, next and phys must all be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * aligned to a section boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (type->prot_sect &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ((addr | next | phys) & ~SECTION_MASK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) __map_init_section(pmd, addr, next, phys, type, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) alloc_init_pte(pmd, addr, next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __phys_to_pfn(phys), type, alloc, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) phys += next - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } while (pmd++, addr = next, addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned long end, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) const struct mem_type *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) void *(*alloc)(unsigned long sz), bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pud_t *pud = pud_offset(p4d, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned long next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) next = pud_addr_end(addr, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) phys += next - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) } while (pud++, addr = next, addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned long end, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) const struct mem_type *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) void *(*alloc)(unsigned long sz), bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) p4d_t *p4d = p4d_offset(pgd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned long next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) next = p4d_addr_end(addr, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) phys += next - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) } while (p4d++, addr = next, addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static void __init create_36bit_mapping(struct mm_struct *mm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct map_desc *md,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) const struct mem_type *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned long addr, length, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pgd_t *pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) addr = md->virtual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) phys = __pfn_to_phys(md->pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) length = PAGE_ALIGN(md->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (long long)__pfn_to_phys((u64)md->pfn), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* N.B. ARMv6 supersections are only defined to work with domain 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * Since domain assignments can in fact be arbitrary, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * 'domain == 0' check below is required to insure that ARMv6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * supersections are only allocated for domain 0 regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * of the actual domain assignments in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (type->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) (long long)__pfn_to_phys((u64)md->pfn), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (long long)__pfn_to_phys((u64)md->pfn), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * Shift bits [35:32] of address into bits [23:20] of PMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * (See ARMv6 spec).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pgd = pgd_offset(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) end = addr + length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) p4d_t *p4d = p4d_offset(pgd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pud_t *pud = pud_offset(p4d, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pmd_t *pmd = pmd_offset(pud, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) (ng ? PMD_SECT_nG : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) addr += SUPERSECTION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) phys += SUPERSECTION_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) } while (addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif /* !CONFIG_ARM_LPAE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void *(*alloc)(unsigned long sz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned long addr, length, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) const struct mem_type *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pgd_t *pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) type = &mem_types[md->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * Catch 36-bit addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (md->pfn >= 0x100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) create_36bit_mapping(mm, md, type, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) addr = md->virtual & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) phys = __pfn_to_phys(md->pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (long long)__pfn_to_phys(md->pfn), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pgd = pgd_offset(mm, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) end = addr + length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned long next = pgd_addr_end(addr, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) phys += next - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) addr = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) } while (pgd++, addr != end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Create the page directory entries and any necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * page tables for the mapping specified by `md'. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * are able to cope here with varying sizes and address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * offsets, and we take full advantage of sections and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * supersections.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static void __init create_mapping(struct map_desc *md)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (md->type == MT_DEVICE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __create_mapping(&init_mm, md, early_alloc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) bool ng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) p4d_t *p4d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pud_t *pud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (WARN_ON(!p4d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pud = pud_alloc(mm, p4d, md->virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (WARN_ON(!pud))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pmd_alloc(mm, pud, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) __create_mapping(mm, md, late_alloc, ng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * Create the architecture specific mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) void __init iotable_init(struct map_desc *io_desc, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct map_desc *md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct vm_struct *vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct static_vm *svm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!svm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __func__, sizeof(*svm) * nr, __alignof__(*svm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) for (md = io_desc; nr; md++, nr--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) create_mapping(md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) vm = &svm->vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) vm->addr = (void *)(md->virtual & PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) vm->phys_addr = __pfn_to_phys(md->pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) vm->flags |= VM_ARM_MTYPE(md->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) vm->caller = iotable_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) add_static_vm_early(svm++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) void *caller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct vm_struct *vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct static_vm *svm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) svm = memblock_alloc(sizeof(*svm), __alignof__(*svm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (!svm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) panic("%s: Failed to allocate %zu bytes align=0x%zx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __func__, sizeof(*svm), __alignof__(*svm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) vm = &svm->vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) vm->addr = (void *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) vm->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) vm->caller = caller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) add_static_vm_early(svm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #ifndef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * The Linux PMD is made of two consecutive section entries covering 2MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * (see definition in include/asm/pgtable-2level.h). However a call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * create_mapping() may optimize static mappings by using individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * 1MB section mappings. This leaves the actual PMD potentially half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * initialized if the top or bottom section entry isn't used, leaving it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * open to problems if a subsequent ioremap() or vmalloc() tries to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * the virtual space left free by that unused section entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * Let's avoid the issue by inserting dummy vm entries covering the unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * PMD halves once the static mappings are in place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void __init pmd_empty_section_gap(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static void __init fill_pmd_gaps(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct static_vm *svm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct vm_struct *vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) unsigned long addr, next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pmd_t *pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) list_for_each_entry(svm, &static_vmlist, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) vm = &svm->vm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) addr = (unsigned long)vm->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (addr < next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * Check if this vm starts on an odd section boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * If so and the first section entry for this PMD is free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * then we block the corresponding virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if ((addr & ~PMD_MASK) == SECTION_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) pmd = pmd_off_k(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (pmd_none(*pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pmd_empty_section_gap(addr & PMD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * Then check if this vm ends on an odd section boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * If so and the second section entry for this PMD is empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * then we block the corresponding virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) addr += vm->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if ((addr & ~PMD_MASK) == SECTION_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pmd = pmd_off_k(addr) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (pmd_none(*pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pmd_empty_section_gap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* no need to look at any vm entry until we hit the next PMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) next = (addr + PMD_SIZE - 1) & PMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define fill_pmd_gaps() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static void __init pci_reserve_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct static_vm *svm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (svm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define pci_reserve_io() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #ifdef CONFIG_DEBUG_LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) void __init debug_ll_io_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct map_desc map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) debug_ll_addr(&map.pfn, &map.virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!map.pfn || !map.virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) map.pfn = __phys_to_pfn(map.pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) map.virtual &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) map.length = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) map.type = MT_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) iotable_init(&map, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static void * __initdata vmalloc_min =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * vmalloc=size forces the vmalloc area to be exactly 'size'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * bytes. This can be used to increase (or decrease) the vmalloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * area - the default is 240m.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static int __init early_vmalloc(char *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) unsigned long vmalloc_reserve = memparse(arg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (vmalloc_reserve < SZ_16M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) vmalloc_reserve = SZ_16M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pr_warn("vmalloc area too small, limiting to %luMB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) vmalloc_reserve >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pr_warn("vmalloc area is too big, limiting to %luMB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) vmalloc_reserve >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) early_param("vmalloc", early_vmalloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) phys_addr_t arm_lowmem_limit __initdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) void __init adjust_lowmem_bounds(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) phys_addr_t block_start, block_end, memblock_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u64 vmalloc_limit, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) phys_addr_t lowmem_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * Let's use our own (unoptimized) equivalent of __pa() that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * not affected by wrap-arounds when sizeof(phys_addr_t) == 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * The result is used as the upper bound on physical memory address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * and may itself be outside the valid range for which phys_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * and therefore __pa() is defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * The first usable region must be PMD aligned. Mark its start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * as MEMBLOCK_NOMAP if it isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) for_each_mem_range(i, &block_start, &block_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!IS_ALIGNED(block_start, PMD_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) phys_addr_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) len = round_up(block_start, PMD_SIZE) - block_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) memblock_mark_nomap(block_start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) for_each_mem_range(i, &block_start, &block_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (block_start < vmalloc_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (block_end > lowmem_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * Compare as u64 to ensure vmalloc_limit does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * not get truncated. block_end should always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * fit in phys_addr_t so there should be no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * issue with assignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) lowmem_limit = min_t(u64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) vmalloc_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) block_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * Find the first non-pmd-aligned page, and point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * memblock_limit at it. This relies on rounding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * limit down to be pmd-aligned, which happens at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * end of this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * With this algorithm, the start or end of almost any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * bank can be non-pmd-aligned. The only exception is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * that the start of the bank 0 must be section-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * aligned, since otherwise memory would need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * allocated when mapping the start of bank 0, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * occurs before any free memory is mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!memblock_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (!IS_ALIGNED(block_start, PMD_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) memblock_limit = block_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) else if (!IS_ALIGNED(block_end, PMD_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) memblock_limit = lowmem_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) arm_lowmem_limit = lowmem_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) high_memory = __va(arm_lowmem_limit - 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (!memblock_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) memblock_limit = arm_lowmem_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Round the memblock limit down to a pmd size. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * helps to ensure that we will allocate memory from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * last full pmd, which should be mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) memblock_limit = round_down(memblock_limit, PMD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (memblock_end_of_DRAM() > arm_lowmem_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) phys_addr_t end = memblock_end_of_DRAM();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) pr_notice("Ignoring RAM at %pa-%pa\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) &memblock_limit, &end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) pr_notice("Consider using a HIGHMEM enabled kernel.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) memblock_remove(memblock_limit, end - memblock_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) memblock_set_current_limit(memblock_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static inline void prepare_page_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) phys_addr_t end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * Clear out all the mappings below the kernel image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) pmd_clear(pmd_off_k(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* The XIP kernel is mapped in the module area -- skip over it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pmd_clear(pmd_off_k(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * Find the end of the first block of lowmem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (end >= arm_lowmem_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) end = arm_lowmem_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * Clear out all the kernel space mappings, except for the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * memory bank, up to the vmalloc region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) for (addr = __phys_to_virt(end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) addr < VMALLOC_START; addr += PMD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) pmd_clear(pmd_off_k(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #ifdef CONFIG_ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* the first page is reserved for pgd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * Reserve the special regions of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) void __init arm_mm_memblock_reserve(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * Reserve the page tables. These are already in use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * and can only be in node 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #ifdef CONFIG_SA1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * Because of the SA1111 DMA bug, we want to preserve our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * precious DMA-able memory...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * Set up the device mappings. Since we clear out the page tables for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * mappings above VMALLOC_START, except early fixmap, we might remove debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * device mappings. This means earlycon can be used to debug this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Any other function or debugging method which may touch any device _will_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * crash the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static void __init devicemaps_init(const struct machine_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct map_desc map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) void *vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * Allocate the vector page early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) vectors = early_alloc(PAGE_SIZE * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) early_trap_init(vectors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * Clear page table except top pmd used by early fixmaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) pmd_clear(pmd_off_k(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (__atags_pointer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* create a read-only mapping of the device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) map.virtual = FDT_FIXED_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) map.length = FDT_FIXED_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) map.type = MT_ROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * Map the kernel if it is XIP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * It is always first in the modulearea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #ifdef CONFIG_XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) map.virtual = MODULES_VADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) map.type = MT_ROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * Map the cache flushing regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #ifdef FLUSH_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) map.virtual = FLUSH_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) map.length = SZ_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) map.type = MT_CACHECLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #ifdef FLUSH_BASE_MINICACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) map.virtual = FLUSH_BASE_MINICACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) map.length = SZ_1M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) map.type = MT_MINICLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * Create a mapping for the machine vectors at the high-vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * location (0xffff0000). If we aren't using high-vectors, also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * create a mapping at the low-vectors virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) map.pfn = __phys_to_pfn(virt_to_phys(vectors));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) map.virtual = 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) map.length = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #ifdef CONFIG_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) map.type = MT_HIGH_VECTORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) map.type = MT_LOW_VECTORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (!vectors_high()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) map.virtual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) map.length = PAGE_SIZE * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) map.type = MT_LOW_VECTORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* Now create a kernel read-only mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) map.pfn += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) map.virtual = 0xffff0000 + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) map.length = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) map.type = MT_LOW_VECTORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * Ask the machine support to map in the statically mapped devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (mdesc->map_io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mdesc->map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) debug_ll_io_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) fill_pmd_gaps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Reserve fixed i/o space in VMALLOC region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) pci_reserve_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * Finally flush the caches and tlb to ensure that we're in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * consistent state wrt the writebuffer. This also ensures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * any write-allocated cache lines in the vector page are written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * back. After this point, we can start to touch devices again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Enable asynchronous aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) early_abt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static void __init kmap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #ifdef CONFIG_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PKMAP_BASE, _PAGE_KERNEL_TABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) _PAGE_KERNEL_TABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static void __init map_lowmem(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) phys_addr_t start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u64 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* Map all the lowmem memory banks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) for_each_mem_range(i, &start, &end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct map_desc map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (end > arm_lowmem_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) end = arm_lowmem_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (start >= end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (end < kernel_x_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) map.pfn = __phys_to_pfn(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) map.virtual = __phys_to_virt(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) map.length = end - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) map.type = MT_MEMORY_RWX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) } else if (start >= kernel_x_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) map.pfn = __phys_to_pfn(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) map.virtual = __phys_to_virt(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) map.length = end - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) map.type = MT_MEMORY_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* This better cover the entire kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (start < kernel_x_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) map.pfn = __phys_to_pfn(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) map.virtual = __phys_to_virt(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) map.length = kernel_x_start - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) map.type = MT_MEMORY_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) map.pfn = __phys_to_pfn(kernel_x_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) map.virtual = __phys_to_virt(kernel_x_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) map.length = kernel_x_end - kernel_x_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) map.type = MT_MEMORY_RWX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (kernel_x_end < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) map.pfn = __phys_to_pfn(kernel_x_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) map.virtual = __phys_to_virt(kernel_x_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) map.length = end - kernel_x_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) map.type = MT_MEMORY_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #ifdef CONFIG_ARM_PV_FIXUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) typedef void pgtables_remap(long long offset, unsigned long pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pgtables_remap lpae_pgtables_remap_asm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * early_paging_init() recreates boot time page table setup, allowing machines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * to switch over to a high (>4G) address space on LPAE systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static void __init early_paging_init(const struct machine_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pgtables_remap *lpae_pgtables_remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) unsigned long pa_pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) unsigned int cr, ttbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) long long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (!mdesc->pv_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) offset = mdesc->pv_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * Get the address of the remap function in the 1:1 identity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * mapping setup by the early page table assembly code. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * must get this prior to the pv update. The following barrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * ensures that this is complete before we fixup any P:V offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) pa_pgd = __pa(swapper_pg_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pr_info("Switching physical address space to 0x%08llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) (u64)PHYS_OFFSET + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Re-set the phys pfn offset, and the pv offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) __pv_offset += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) __pv_phys_pfn_offset += PFN_DOWN(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* Run the patch stub to update the constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) fixup_pv_table(&__pv_table_begin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) (&__pv_table_end - &__pv_table_begin) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * We changing not only the virtual to physical mapping, but also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * the physical addresses used to access memory. We need to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * all levels of cache in the system with caching disabled to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * ensure that all data is written back, and nothing is prefetched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * into the caches. We also need to prevent the TLB walkers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * allocating into the caches too. Note that this is ARMv7 LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) cr = get_cr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) set_cr(cr & ~(CR_I | CR_C));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) asm volatile("mcr p15, 0, %0, c2, c0, 2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * Fixup the page tables - this must be in the idmap region as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * we need to disable the MMU to do this safely, and hence it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * needs to be assembly. It's fairly simple, as we're using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * temporary tables setup by the initial assembly code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) lpae_pgtables_remap(offset, pa_pgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* Re-enable the caches and cacheable TLB walks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) set_cr(cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static void __init early_paging_init(const struct machine_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) long long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (!mdesc->pv_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) offset = mdesc->pv_fixup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pr_crit("Physical address space modification is only to support Keystone2.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) pr_crit("feature. Your kernel may crash now, have a good day.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static void __init early_fixmap_shutdown(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) pte_offset_fixmap = pte_offset_late_fixmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) pmd_clear(fixmap_pmd(va));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) local_flush_tlb_kernel_page(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) pte_t *pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct map_desc map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) map.virtual = fix_to_virt(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* Only i/o device mappings are supported ATM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (pte_none(*pte) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) map.pfn = pte_pfn(*pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) map.type = MT_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) map.length = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) create_mapping(&map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * paging_init() sets up the page tables, initialises the zone memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * maps, and sets up the zero page, bad page and bad page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) void __init paging_init(const struct machine_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) void *zero_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) prepare_page_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) map_lowmem();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) memblock_set_current_limit(arm_lowmem_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) dma_contiguous_remap();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) early_fixmap_shutdown();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) devicemaps_init(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) kmap_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) tcm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) top_pmd = pmd_off_k(0xffff0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* allocate the zero page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) zero_page = early_alloc(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) bootmem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) empty_zero_page = virt_to_page(zero_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) __flush_dcache_page(NULL, empty_zero_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) void __init early_mm_init(const struct machine_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) build_mem_type_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) early_paging_init(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) void set_pte_at(struct mm_struct *mm, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) pte_t *ptep, pte_t pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) unsigned long ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (addr < TASK_SIZE && pte_valid_user(pteval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (!pte_special(pteval))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) __sync_icache_dcache(pteval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ext |= PTE_EXT_NG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) set_pte_ext(ptep, pteval, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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