Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * L2C-310 early resume code.  This can be used by platforms to restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * the settings of their L2 cache controller before restoring the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * processor state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * This code can only be used to if you are running in the secure world.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ENTRY(l2c310_early_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	adr	r0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	ldr	r2, [r0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	add	r0, r2, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	ldmia	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	@ r1 = phys address of L2C-310 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	@ r2 = aux_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	@ r3 = tag_latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	@ r4 = data_latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	@ r5 = filter_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	@ r6 = filter_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	@ r7 = prefetch_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	@ r8 = pwr_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	@ Check that the address has been initialised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	teq	r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reteq	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	@ The prefetch and power control registers are revision dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	@ and can be written whether or not the L2 cache is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	ldr	r0, [r1, #L2X0_CACHE_ID]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	and	r0, r0, #L2X0_CACHE_ID_RTL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	cmp	r0, #L310_CACHE_ID_RTL_R2P0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	strcs	r7, [r1, #L310_PREFETCH_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	cmp	r0, #L310_CACHE_ID_RTL_R3P0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	strcs	r8, [r1, #L310_POWER_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	@ Don't setup the L2 cache if it is already enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	ldr	r0, [r1, #L2X0_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	tst	r0, #L2X0_CTRL_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	retne	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	str	r3, [r1, #L310_TAG_LATENCY_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	str	r4, [r1, #L310_DATA_LATENCY_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	str	r6, [r1, #L310_ADDR_FILTER_END]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	str	r5, [r1, #L310_ADDR_FILTER_START]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	str	r2, [r1, #L2X0_AUX_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	mov	r9, #L2X0_CTRL_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	str	r9, [r1, #L2X0_CTRL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	ret	lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ENDPROC(l2c310_early_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	.align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 1:	.long	l2x0_saved_regs - .