^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/lib/copypage-armv4mc.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2005 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This handles the mini data cache, as found on SA11x0 and XScale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * processors. When we copy a user page page, we map it in such a way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * that accesses to this page will not touch the main data cache, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * will be cached in the mini data cache. This prevents us thrashing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the main data cache on page faults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "mm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) L_PTE_MT_MINICACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static DEFINE_RAW_SPINLOCK(minicache_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ARMv4 mini-dcache optimised copy_user_highpage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * We flush the destination cache lines just before we write the data into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * corresponding address. Since the Dcache is read-allocate, this removes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Dcache aliasing issue. The writes will be forwarded to the write buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * and merged as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * instruction. If your processor does not supply this, you have to write your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * own copy_user_highpage that does the right thing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void mc_copy_user_page(void *from, void *to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) asm volatile ("\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .syntax unified\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ldmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) stmia %1!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) stmia %1!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ldmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) stmia %1!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ldmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) subs %2, %2, #1 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) stmia %1!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ldmiane %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bne 1b @ "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) : "+&r" (from), "+&r" (to), "=&r" (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) : "2" (PAGE_SIZE / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) : "r2", "r3", "ip", "lr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void v4_mc_copy_user_highpage(struct page *to, struct page *from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long vaddr, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void *kto = kmap_atomic(to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!test_and_set_bit(PG_dcache_clean, &from->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __flush_dcache_page(page_mapping_file(from), from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) raw_spin_lock(&minicache_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_spin_unlock(&minicache_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) kunmap_atomic(kto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ARMv4 optimised clear_user_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void *ptr, *kaddr = kmap_atomic(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) asm volatile("\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mov r1, %2 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mov r2, #0 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mov r3, #0 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mov ip, #0 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mov lr, #0 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) stmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) stmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) stmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) stmia %0!, {r2, r3, ip, lr} @ 4\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) subs r1, r1, #1 @ 1\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bne 1b @ 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) : "=r" (ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) : "0" (kaddr), "I" (PAGE_SIZE / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : "r1", "r2", "r3", "ip", "lr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) kunmap_atomic(kaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct cpu_user_fns v4_mc_user_fns __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .cpu_clear_user_highpage = v4_mc_clear_user_highpage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .cpu_copy_user_highpage = v4_mc_copy_user_highpage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags