^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Tauros3 cache controller includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on GPL'ed 2.6 kernel sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (c) Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __ASM_ARM_HARDWARE_TAUROS3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __ASM_ARM_HARDWARE_TAUROS3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Marvell Tauros3 L2CC is compatible with PL310 r0p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * but with PREFETCH_CTRL (r2p0) and an additional event counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Also, there is AUX2_CTRL for some Marvell specific control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TAUROS3_EVENT_CNT2_CFG 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TAUROS3_EVENT_CNT2_VAL 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TAUROS3_INV_ALL 0x780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TAUROS3_CLEAN_ALL 0x784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TAUROS3_AUX2_CTRL 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Registers shifts and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif