^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - Unified Layer 2 Cache for Feroceon CPU Cores,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Document ID MV-S104858-00, Rev. A, October 23 2007.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/hardware/cache-feroceon-l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define L2_WRITETHROUGH_KIRKWOOD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Low-level cache maintenance operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * As well as the regular 'clean/invalidate/flush L2 cache line by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * MVA' instructions, the Feroceon L2 cache controller also features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 'clean/invalidate L2 range by MVA' operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Cache range operations are initiated by writing the start and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * end addresses to successive cp15 registers, and process every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * cache line whose first byte address lies in the inclusive range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * [start:end].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The cache range operations stall the CPU pipeline until completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The range operations require two successive cp15 writes, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * between which we don't want to be preempted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline unsigned long l2_get_va(unsigned long paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Because range ops can't be done on physical addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * we simply install a virtual mapping for it only for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * TLB lookup to occur, hence no need to flush the untouched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * memory mapping afterwards (note: a cache flush may happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * in some circumstances depending on the path taken in kunmap_atomic).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return (unsigned long)vaddr + (paddr & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return __phys_to_virt(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline void l2_put_va(unsigned long vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) kunmap_atomic((void *)vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline void l2_clean_pa(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long va_start, va_end, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Make sure 'start' and 'end' reference the same page, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * L2 is PIPT and range operations only do a TLB lookup on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * the start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BUG_ON((start ^ end) >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) va_start = l2_get_va(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) va_end = va_start + (end - start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) raw_local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __asm__("mcr p15, 1, %0, c15, c9, 4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "mcr p15, 1, %1, c15, c9, 5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) : : "r" (va_start), "r" (va_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) raw_local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) l2_put_va(va_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline void l2_clean_inv_pa(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline void l2_inv_pa(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long va_start, va_end, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Make sure 'start' and 'end' reference the same page, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * L2 is PIPT and range operations only do a TLB lookup on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * the start address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BUG_ON((start ^ end) >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) va_start = l2_get_va(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) va_end = va_start + (end - start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) raw_local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __asm__("mcr p15, 1, %0, c15, c11, 4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "mcr p15, 1, %1, c15, c11, 5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) : : "r" (va_start), "r" (va_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) raw_local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) l2_put_va(va_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void l2_inv_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Linux primitives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Note that the end addresses passed to Linux primitives are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * noninclusive, while the hardware cache range operations use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * inclusive start and end addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CACHE_LINE_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MAX_RANGE_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int l2_wt_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static unsigned long calc_range_end(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long range_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) BUG_ON(start & (CACHE_LINE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) BUG_ON(end & (CACHE_LINE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Try to process all cache lines between 'start' and 'end'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) range_end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Limit the number of cache lines processed at once,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * since cache range operations stall the CPU pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * until completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (range_end > start + MAX_RANGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) range_end = start + MAX_RANGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Cache range operations can't straddle a page boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (range_end > (start | (PAGE_SIZE - 1)) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) range_end = (start | (PAGE_SIZE - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return range_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Clean and invalidate partial first cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (start & (CACHE_LINE_SIZE - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) start = (start | (CACHE_LINE_SIZE - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Clean and invalidate partial last cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (start < end && end & (CACHE_LINE_SIZE - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) end &= ~(CACHE_LINE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Invalidate all full cache lines between 'start' and 'end'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (start < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long range_end = calc_range_end(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) start = range_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * If L2 is forced to WT, the L2 will always be clean and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * don't need to do anything here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!l2_wt_override) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) start &= ~(CACHE_LINE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) while (start != end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long range_end = calc_range_end(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) start = range_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) start &= ~(CACHE_LINE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) while (start != end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long range_end = calc_range_end(start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!l2_wt_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) start = range_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Routines to disable and re-enable the D-cache and I-cache at run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * time. These are necessary because the L2 cache can only be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * or disabled while the L1 Dcache and Icache are both disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int __init flush_and_disable_dcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cr = get_cr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (cr & CR_C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) raw_local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) set_cr(cr & ~CR_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) raw_local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void __init enable_dcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cr = get_cr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) set_cr(cr | CR_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void __init __invalidate_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int __init invalidate_and_disable_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cr = get_cr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (cr & CR_I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) set_cr(cr & ~CR_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __invalidate_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void __init enable_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cr = get_cr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) set_cr(cr | CR_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline u32 read_extra_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static inline void write_extra_features(u32 u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void __init disable_l2_prefetch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Read the CPU Extra Features register and verify that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Disable L2 Prefetch bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u = read_extra_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!(u & 0x01000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pr_info("Feroceon L2: Disabling L2 prefetch.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) write_extra_features(u | 0x01000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void __init enable_l2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u = read_extra_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!(u & 0x00400000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int i, d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pr_info("Feroceon L2: Enabling L2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) d = flush_and_disable_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) i = invalidate_and_disable_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) l2_inv_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) write_extra_features(u | 0x00400000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enable_icache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enable_dcache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pr_err(FW_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Feroceon L2: bootloader left the L2 cache on!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __init feroceon_l2_init(int __l2_wt_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) l2_wt_override = __l2_wt_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) disable_l2_prefetch();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) outer_cache.inv_range = feroceon_l2_inv_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) outer_cache.clean_range = feroceon_l2_clean_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) outer_cache.flush_range = feroceon_l2_flush_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enable_l2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) pr_info("Feroceon L2: Cache support initialised%s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) l2_wt_override ? ", in WT override mode" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct of_device_id feroceon_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .compatible = "marvell,kirkwood-cache"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .compatible = "marvell,feroceon-cache"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int __init feroceon_of_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bool l2_wt_override = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) l2_wt_override = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) node = of_find_matching_node(NULL, feroceon_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (l2_wt_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) feroceon_l2_init(l2_wt_override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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