Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Function: v4t_late_abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Params  : r2 = pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	   : r4 = aborted context pc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	   : r5 = aborted context psr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Returns : r4-r5, r9-r11, r13 preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Purpose : obtain information about current aborted instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Note: we read user space.  This means we might cause a data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * abort here if the I-TLB and D-TLB aren't seeing the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * picture.  Unfortunately, this does happen.  We live with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) ENTRY(v4t_late_abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	tst	r5, #PSR_T_BIT			@ check for thumb mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #ifdef CONFIG_CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	mov	r0, #0				@ clear r0, r1 (no FSR/FAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	mov	r1, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	bne	.data_thumb_abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	ldr	r8, [r4]			@ read arm instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	uaccess_disable ip			@ disable userspace access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	tst	r8, #1 << 20			@ L = 1 -> write?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	orreq	r1, r1, #1 << 11		@ yes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	and	r7, r8, #15 << 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	add	pc, pc, r7, lsr #22		@ Now branch to the relevant processing routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* 0 */	b	.data_arm_lateldrhpost		@ ldrh	rd, [rn], #m/rm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* 1 */	b	.data_arm_lateldrhpre		@ ldrh	rd, [rn, #m/rm]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* 2 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* 3 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* 4 */	b	.data_arm_lateldrpostconst	@ ldr	rd, [rn], #m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* 5 */	b	.data_arm_lateldrpreconst	@ ldr	rd, [rn, #m] 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* 6 */	b	.data_arm_lateldrpostreg	@ ldr	rd, [rn], rm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* 7 */	b	.data_arm_lateldrprereg		@ ldr	rd, [rn, rm]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* 8 */	b	.data_arm_ldmstm		@ ldm*a	rn, <rlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* 9 */	b	.data_arm_ldmstm		@ ldm*b	rn, <rlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* a */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* b */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* c */	b	do_DataAbort			@ ldc	rd, [rn], #m	@ Same as ldr	rd, [rn], #m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* d */	b	do_DataAbort			@ ldc	rd, [rn, #m]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* e */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* f */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) .data_unknown_r9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ldr	r9, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) .data_unknown:	@ Part of jumptable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mov	r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mov	r1, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	b	baddataabort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) .data_arm_ldmstm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	tst	r8, #1 << 21			@ check writeback bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	beq	do_DataAbort			@ no writeback -> no fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	str	r9, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	mov	r7, #0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	orr	r7, r7, #0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	and	r6, r8, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	and	r9, r8, r7, lsl #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	add	r6, r6, r9, lsr #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	and	r9, r8, r7, lsl #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	add	r6, r6, r9, lsr #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	and	r9, r8, r7, lsl #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	add	r6, r6, r9, lsr #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	add	r6, r6, r6, lsr #8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	add	r6, r6, r6, lsr #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	and	r6, r6, #15			@ r6 = no. of registers to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	tst	r8, #1 << 23			@ Check U bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	subne	r7, r7, r6, lsl #2		@ Undo increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	addeq	r7, r7, r6, lsl #2		@ Undo decrement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ldr	r9, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) .data_arm_lateldrhpre:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	tst	r8, #1 << 21			@ Check writeback bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	beq	do_DataAbort			@ No writeback -> no fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) .data_arm_lateldrhpost:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	str	r9, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	and	r9, r8, #0x00f			@ get Rm / low nibble of immediate value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	tst	r8, #1 << 22			@ if (immediate offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	andne	r6, r8, #0xf00			@ { immediate high nibble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	orrne	r6, r9, r6, lsr #4		@   combine nibbles } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ldreq	r6, [r2, r9, lsl #2]		@ { load Rm value }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) .data_arm_apply_r6_and_rn:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	tst	r8, #1 << 23			@ Check U bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	subne	r7, r7, r6			@ Undo incrmenet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	addeq	r7, r7, r6			@ Undo decrement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	ldr	r9, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .data_arm_lateldrpreconst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tst	r8, #1 << 21			@ check writeback bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	beq	do_DataAbort			@ no writeback -> no fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .data_arm_lateldrpostconst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	movs	r6, r8, lsl #20			@ Get offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	beq	do_DataAbort			@ zero -> no fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	str	r9, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	and	r9, r8, #15 << 16		@ Extract 'n' from instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ldr	r7, [r2, r9, lsr #14]		@ Get register 'Rn'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	tst	r8, #1 << 23			@ Check U bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	subne	r7, r7, r6, lsr #20		@ Undo increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	addeq	r7, r7, r6, lsr #20		@ Undo decrement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	str	r7, [r2, r9, lsr #14]		@ Put register 'Rn'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ldr	r9, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .data_arm_lateldrprereg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	tst	r8, #1 << 21			@ check writeback bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	beq	do_DataAbort			@ no writeback -> no fixup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .data_arm_lateldrpostreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	and	r7, r8, #15			@ Extract 'm' from instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ldr	r6, [r2, r7, lsl #2]		@ Get register 'Rm'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	str	r9, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mov	r9, r8, lsr #7			@ get shift count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ands	r9, r9, #31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	and	r7, r8, #0x70			@ get shift type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	orreq	r7, r7, #8			@ shift count = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	add	pc, pc, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mov	r6, r6, lsl r9			@ 0: LSL #!0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	b	.data_arm_apply_r6_and_rn	@ 1: LSL #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	b	.data_unknown_r9		@ 2: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	b	.data_unknown_r9		@ 3: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mov	r6, r6, lsr r9			@ 4: LSR #!0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	mov	r6, r6, lsr #32			@ 5: LSR #32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	b	.data_unknown_r9		@ 6: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	b	.data_unknown_r9		@ 7: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mov	r6, r6, asr r9			@ 8: ASR #!0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mov	r6, r6, asr #32			@ 9: ASR #32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	b	.data_unknown_r9		@ A: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	b	.data_unknown_r9		@ B: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	mov	r6, r6, ror r9			@ C: ROR #!0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	mov	r6, r6, rrx			@ D: RRX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	b	.data_arm_apply_r6_and_rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	b	.data_unknown_r9		@ E: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	b	.data_unknown_r9		@ F: MUL?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .data_thumb_abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ldrh	r8, [r4]			@ read instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	uaccess_disable ip			@ disable userspace access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	tst	r8, #1 << 11			@ L = 1 -> write?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	orreq	r1, r1, #1 << 8			@ yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	and	r7, r8, #15 << 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	add	pc, pc, r7, lsr #10		@ lookup in table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 0 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 1 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* 2 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* 3 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* 4 */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* 5 */	b	.data_thumb_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* 6 */	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* 7 */	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* 8 */	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* 9 */	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* A */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* B */	b	.data_thumb_pushpop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* C */	b	.data_thumb_ldmstm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* D */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* E */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* F */	b	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .data_thumb_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	tst	r8, #1 << 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	beq	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	tst	r8, #1 << 10			@ If 'S' (signed) bit is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	movne	r1, #0				@ it must be a load instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .data_thumb_pushpop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	tst	r8, #1 << 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	beq	.data_unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	str	r9, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	and	r6, r8, #0x55			@ hweight8(r8) + R bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	and	r9, r8, #0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	add	r6, r6, r9, lsr #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	and	r9, r6, #0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	and	r6, r6, #0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	add	r6, r6, r9, lsr #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	movs	r7, r8, lsr #9			@ C = r8 bit 8 (R bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	adc	r6, r6, r6, lsr #4		@ high + low nibble + R bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	and	r6, r6, #15			@ number of regs to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	ldr	r7, [r2, #13 << 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	tst	r8, #1 << 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	addeq	r7, r7, r6, lsl #2		@ increment SP if PUSH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	subne	r7, r7, r6, lsl #2		@ decrement SP if POP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	str	r7, [r2, #13 << 2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ldr	r9, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	b	do_DataAbort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .data_thumb_ldmstm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	str	r9, [sp, #-4]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	and	r6, r8, #0x55			@ hweight8(r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	and	r9, r8, #0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	add	r6, r6, r9, lsr #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	and	r9, r6, #0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	and	r6, r6, #0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	add	r6, r6, r9, lsr #2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	add	r6, r6, r6, lsr #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	and	r9, r8, #7 << 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ldr	r7, [r2, r9, lsr #6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	and	r6, r6, #15			@ number of regs to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	sub	r7, r7, r6, lsl #2		@ always decrement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	str	r7, [r2, r9, lsr #6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	ldr	r9, [sp], #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	b	do_DataAbort