Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include "abort-macro.S"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Function: v6_early_abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Params  : r2 = pt_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *	   : r4 = aborted context pc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *	   : r5 = aborted context psr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * Returns : r4 - r11, r13 preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Purpose : obtain information about current aborted instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Note: we read user space.  This means we might cause a data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * abort here if the I-TLB and D-TLB aren't seeing the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * picture.  Unfortunately, this does happen.  We live with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ENTRY(v6_early_abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_ARM_ERRATA_326103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	ldr	ip, =0x4107b36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	mrc	p15, 0, r3, c0, c0, 0		@ get processor id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	teq	ip, r3, lsr #4			@ r0 ARM1136?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	bne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	tst	r5, #PSR_J_BIT			@ Java?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	tsteq	r5, #PSR_T_BIT			@ Thumb?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	bne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	bic	r1, r1, #1 << 11		@ clear bit 11 of FSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	ldr	r3, [r4]			@ read aborted ARM instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  ARM_BE8(rev	r3, r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	teq_ldrd tmp=ip, insn=r3		@ insn was LDRD?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	beq	1f				@ yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	tst	r3, #1 << 20			@ L = 0 -> write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	orreq	r1, r1, #1 << 11		@ yes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 1:	uaccess_disable ip			@ disable userspace access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	b	do_DataAbort