^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) comment "Processor Type"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) # Select CPU types depending on the architecture selected. This selects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) # which CPUs we support in the kernel image, and the compiler instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) # optimiser behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) # ARM7TDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) config CPU_ARM7TDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) select CPU_ABRT_LV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) select CPU_CACHE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) A 32-bit RISC microprocessor based on the ARM7 processor core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) which has no memory control unit and cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Say Y if you want support for the ARM7TDMI processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) # ARM720T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) config CPU_ARM720T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) select CPU_ABRT_LV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) select CPU_CACHE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) select CPU_COPY_V4WT if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) select CPU_TLB_V4WT if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) A 32-bit RISC processor with 8kByte Cache, Write Buffer and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MMU built around an ARM7TDMI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Say Y if you want support for the ARM720T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # ARM740T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) config CPU_ARM740T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) select CPU_ABRT_LV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) select CPU_CACHE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) select CPU_CP15_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) A 32-bit RISC processor with 8KB cache or 4KB variants,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) write buffer and MPU(Protection Unit) built around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) an ARM7TDMI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Say Y if you want support for the ARM740T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # ARM9TDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) config CPU_ARM9TDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) select CPU_ABRT_NOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) select CPU_CACHE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) A 32-bit RISC microprocessor based on the ARM9 processor core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) which has no memory control unit and cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Say Y if you want support for the ARM9TDMI processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # ARM920T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) config CPU_ARM920T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) select CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) select CPU_CACHE_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) The ARM920T is licensed to be produced by numerous vendors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) and is used in the Cirrus EP93xx and the Samsung S3C2410.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Say Y if you want support for the ARM920T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # ARM922T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) config CPU_ARM922T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) select CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) select CPU_CACHE_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) The ARM922T is a version of the ARM920T, but with smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) instruction and data caches. It is used in Altera's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Excalibur XA device family and the ARM Integrator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Say Y if you want support for the ARM922T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # ARM925T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) config CPU_ARM925T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) select CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) select CPU_CACHE_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) The ARM925T is a mix between the ARM920T and ARM926T, but with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) different instruction and data caches. It is used in TI's OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) device family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) Say Y if you want support for the ARM925T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # ARM926T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config CPU_ARM926T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) select CPU_ABRT_EV5TJ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) This is a variant of the ARM920. It has slightly different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) instruction sequences for cache and TLB operations. Curiously,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) there is no documentation on it at the ARM corporate website.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) Say Y if you want support for the ARM926T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # FA526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) config CPU_FA526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) select CPU_32v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) select CPU_ABRT_EV4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) select CPU_CACHE_FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) select CPU_COPY_FA if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) select CPU_TLB_FA if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) The FA526 is a version of the ARMv4 compatible processor with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Branch Target Buffer, Unified TLB and cache line size 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Say Y if you want support for the FA526 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) # ARM940T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) config CPU_ARM940T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) select CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) select CPU_ABRT_NOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) select CPU_CP15_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ARM940T is a member of the ARM9TDMI family of general-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) purpose microprocessors with MPU and separate 4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) instruction and 4KB data cases, each with a 4-word line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) Say Y if you want support for the ARM940T processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) # ARM946E-S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) config CPU_ARM946E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) select CPU_ABRT_NOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) select CPU_CP15_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ARM946E-S is a member of the ARM9E-S family of high-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) performance, 32-bit system-on-chip processor solutions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) The TCM and ARMv5TE 32-bit instruction set is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) Say Y if you want support for the ARM946E-S processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) # ARM1020 - needs validating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) config CPU_ARM1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) select CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) select CPU_CACHE_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) The ARM1020 is the 32K cached version of the ARM10 processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) with an addition of a floating-point unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) Say Y if you want support for the ARM1020 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) # ARM1020E - needs validating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) config CPU_ARM1020E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) depends on n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) select CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) select CPU_CACHE_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # ARM1022E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) config CPU_ARM1022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) select CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) select CPU_COPY_V4WB if MMU # can probably do better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) The ARM1022E is an implementation of the ARMv5TE architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) embedded trace macrocell, and a floating-point unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) Say Y if you want support for the ARM1022E processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) # ARM1026EJ-S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) config CPU_ARM1026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) select CPU_COPY_V4WB if MMU # can probably do better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) based upon the ARM10 integer core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) Say Y if you want support for the ARM1026EJ-S processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) # SA110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) config CPU_SA110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) select CPU_32v3 if ARCH_RPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) select CPU_32v4 if !ARCH_RPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) select CPU_ABRT_EV4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) select CPU_CACHE_V4WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) select CPU_TLB_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) is available at five speeds ranging from 100 MHz to 233 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) More information is available at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) <http://developer.intel.com/design/strong/sa110.htm>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) Say Y if you want support for the SA-110 processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) Otherwise, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) # SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) config CPU_SA1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) select CPU_32v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) select CPU_ABRT_EV4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) select CPU_CACHE_V4WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) select CPU_TLB_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # XScale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) config CPU_XSCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) select CPU_ABRT_EV5T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) # XScale Core Version 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) config CPU_XSC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) select CPU_ABRT_EV5T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) select IO_36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) # Marvell PJ1 (Mohawk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) config CPU_MOHAWK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) select CPU_ABRT_EV5T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) select CPU_COPY_V4WB if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) select CPU_TLB_V4WBI if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) # Feroceon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) config CPU_FEROCEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) select CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) select CPU_ABRT_EV5T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) select CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) select CPU_COPY_FEROCEON if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) select CPU_TLB_FEROCEON if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) config CPU_FEROCEON_OLD_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) bool "Accept early Feroceon cores with an ARM926 ID"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) depends on CPU_FEROCEON && !CPU_ARM926T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) This enables the usage of some old Feroceon cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for which the CPU ID is equal to the ARM926 ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) Relevant for Feroceon-1850 and early Feroceon-2850.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) # Marvell PJ4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) config CPU_PJ4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) select ARM_THUMBEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) select CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) config CPU_PJ4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) select CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) # ARMv6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) config CPU_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) select CPU_32v6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) select CPU_ABRT_EV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) select CPU_CACHE_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) select CPU_CACHE_VIPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) select CPU_COPY_V6 if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) select CPU_HAS_ASID if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) select CPU_PABRT_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) select CPU_TLB_V6 if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) # ARMv6k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) config CPU_V6K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) select CPU_32v6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) select CPU_32v6K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) select CPU_ABRT_EV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) select CPU_CACHE_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) select CPU_CACHE_VIPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) select CPU_COPY_V6 if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) select CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) select CPU_HAS_ASID if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) select CPU_PABRT_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) select CPU_TLB_V6 if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) # ARMv7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) config CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) select CPU_32v6K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) select CPU_32v7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) select CPU_ABRT_EV7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) select CPU_CACHE_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) select CPU_CACHE_VIPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) select CPU_COPY_V6 if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) select CPU_CP15_MMU if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) select CPU_CP15_MPU if !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) select CPU_HAS_ASID if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) select CPU_PABRT_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) select CPU_SPECTRE if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) select CPU_TLB_V7 if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) # ARMv7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) config CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) select CPU_32v7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) select CPU_ABRT_NOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) select CPU_CACHE_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) select CPU_CACHE_NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) select CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) select CPU_THUMBONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) config CPU_THUMBONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) select CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) # There are no CPUs available with MMU that don't implement an ARM ISA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) Select this if your CPU doesn't support the 32 bit ARM instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) config CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) Select this if your CPU can support Thumb mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) # Figure out what processor architecture version we should be using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) # This defines the compiler instruction set which depends on the machine type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) config CPU_32v3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) select CPU_USE_DOMAINS if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) select NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) select TLS_REG_EMUL if SMP || !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) select CPU_NO_EFFICIENT_FFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) config CPU_32v4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) select CPU_USE_DOMAINS if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) select NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) select TLS_REG_EMUL if SMP || !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) select CPU_NO_EFFICIENT_FFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) config CPU_32v4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) select CPU_USE_DOMAINS if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) select NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) select TLS_REG_EMUL if SMP || !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) select CPU_NO_EFFICIENT_FFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) config CPU_32v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) select CPU_USE_DOMAINS if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) select NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) select TLS_REG_EMUL if SMP || !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) config CPU_32v6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) select TLS_REG_EMUL if !CPU_32v6K && !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) config CPU_32v6K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) config CPU_32v7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) config CPU_32v7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) # The abort model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) config CPU_ABRT_NOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) config CPU_ABRT_EV4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) config CPU_ABRT_EV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) config CPU_ABRT_LV4T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) config CPU_ABRT_EV5T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) config CPU_ABRT_EV5TJ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) config CPU_ABRT_EV6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) config CPU_ABRT_EV7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) config CPU_PABRT_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) config CPU_PABRT_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) config CPU_PABRT_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) # The cache model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) config CPU_CACHE_V4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) config CPU_CACHE_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) config CPU_CACHE_V4WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) config CPU_CACHE_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) config CPU_CACHE_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) config CPU_CACHE_NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) config CPU_CACHE_VIVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) config CPU_CACHE_VIPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) config CPU_CACHE_FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) config CPU_CACHE_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) # The copy-page model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) config CPU_COPY_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) config CPU_COPY_V4WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) config CPU_COPY_FEROCEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) config CPU_COPY_FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) config CPU_COPY_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) # This selects the TLB model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) config CPU_TLB_V4WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ARM Architecture Version 4 TLB with writethrough cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) config CPU_TLB_V4WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ARM Architecture Version 4 TLB with writeback cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) config CPU_TLB_V4WBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ARM Architecture Version 4 TLB with writeback cache and invalidate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) instruction cache entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) config CPU_TLB_FEROCEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) Feroceon TLB (v4wbi with non-outer-cachable page table walks).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) config CPU_TLB_FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) Faraday ARM FA526 architecture, unified TLB with writeback cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) and invalidate instruction cache entry. Branch target buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) also supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) config CPU_TLB_V6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) config CPU_TLB_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) config VERIFY_PERMISSION_FAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) config CPU_HAS_ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) This indicates whether the CPU has the ASID register; used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tag TLB and possibly cache entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) config CPU_CP15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) Processor has the CP15 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) config CPU_CP15_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) select CPU_CP15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) Processor has the CP15 register, which has MMU related registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) config CPU_CP15_MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) select CPU_CP15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) Processor has the CP15 register, which has MPU related registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) config CPU_USE_DOMAINS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) This option enables or disables the use of domain switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) via the set_fs() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) config CPU_V7M_NUM_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int "Number of external interrupts connected to the NVIC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) depends on CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) default 90 if ARCH_STM32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) default 38 if ARCH_EFM32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) default 112 if SOC_VF610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) default 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) This option indicates the number of interrupts connected to the NVIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) The value can be larger than the real number of interrupts supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) by the system, but must not be lower.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) The default value is 240, corresponding to the maximum number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) interrupts supported by the NVIC on Cortex-M family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) If unsure, keep default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) # CPU supports 36-bit I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) config IO_36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) comment "Processor Features"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) config ARM_LPAE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bool "Support for the Large Physical Address Extension"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) !CPU_32v4 && !CPU_32v3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) select PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) select SWIOTLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) Say Y if you have an ARMv7 processor supporting the LPAE page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) table format and you would like to access memory beyond the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 4GB limit. The resulting kernel image will not run on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) processors without the LPA extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) config ARM_PV_FIXUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) config ARM_THUMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) depends on CPU_THUMB_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) Say Y if you want to include kernel support for running user space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) Thumb binaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) The Thumb instruction set is a compressed form of the standard ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) instruction set resulting in smaller binaries at the expense of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) slightly less efficient code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) If this option is disabled, and you run userspace that switches to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) Thumb mode, signal handling will not work correctly, resulting in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) segmentation faults or illegal instruction aborts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) If you don't know what this all is, saying Y is a safe choice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) config ARM_THUMBEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bool "Enable ThumbEE CPU extension"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) depends on CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) Say Y here if you have a CPU with the ThumbEE extension and code to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) make use of it. Say N for code that can run on CPUs without ThumbEE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) config ARM_VIRT_EXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) default y if CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) Enable the kernel to make use of the ARM Virtualization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) Extensions to install hypervisors without run-time firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) assistance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) A compliant bootloader is required in order to make maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) use of this feature. Refer to Documentation/arm/booting.rst for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) config SWP_EMULATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bool "Emulate SWP/SWPB instructions" if !SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) depends on CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) default y if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) select HAVE_PROC_CPU if PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ARMv6 architecture deprecates use of the SWP/SWPB instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ARMv7 multiprocessing extensions introduce the ability to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) these instructions, triggering an undefined instruction exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) when executed. Say Y here to enable software emulation of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) instructions for userspace (not kernel) using LDREX/STREX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) Also creates /proc/cpu/swp_emulation for statistics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) In some older versions of glibc [<=2.8] SWP is used during futex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) trylock() operations with the assumption that the code will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) be preempted. This invalid assumption may be more likely to fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) with SWP emulation enabled, leading to deadlock of the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) application.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) NOTE: when accessing uncached shared regions, LDREX/STREX rely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) on an external transaction monitoring block called a global
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) monitor to maintain update atomicity. If your system does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) implement a global monitor, this option can cause programs that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) perform SWP operations to uncached memory to deadlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) If unsure, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) config CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bool "Build big-endian kernel"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) depends on ARCH_SUPPORTS_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) depends on !LD_IS_LLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) Say Y if you plan on running a kernel in big-endian mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) Note that your board must be properly built and your board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) port must properly enable any big-endian related features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) of your chipset/board/processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) config CPU_ENDIAN_BE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) depends on CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) config CPU_ENDIAN_BE32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) depends on CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) default !CPU_ENDIAN_BE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) config CPU_HIGH_VECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) depends on !MMU && CPU_CP15 && !CPU_ARM740T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) bool "Select the High exception vector"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) Say Y here to select high exception vector(0xFFFF0000~).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) The exception vector can vary depending on the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) design in nommu mode. If your platform needs to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) high exception vector, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) Otherwise or if you are unsure, say N, and the low exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) vector (0x00000000~) will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) config CPU_ICACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) bool "Disable I-Cache (I-bit)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) Say Y here to disable the processor instruction cache. Unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) you have a reason not to or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) config CPU_ICACHE_MISMATCH_WORKAROUND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) bool "Workaround for I-Cache line size mismatch between CPU cores"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) depends on SMP && CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) Some big.LITTLE systems have I-Cache line size mismatch between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) LITTLE and big cores. Say Y here to enable a workaround for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) proper I-Cache support on such systems. If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) config CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) bool "Disable D-Cache (C-bit)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) depends on (CPU_CP15 && !SMP) || CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) Say Y here to disable the processor data cache. Unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) you have a reason not to or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) config CPU_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) hex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) depends on CPU_ARM740T || CPU_ARM946E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) default 0x00001000 if CPU_ARM740T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) default 0x00002000 # default size for ARM946E-S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) Some cores are synthesizable to have various sized cache. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ARM946E-S case, it can vary from 0KB to 1MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) To support such cache operations, it is efficient to know the size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) before compile time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) If your SoC is configured to have a different size, define the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) here with proper conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) config CPU_DCACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) bool "Force write through D-cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) default y if CPU_ARM925T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) Say Y here to use the data cache in writethrough mode. Unless you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) specifically require this or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) config CPU_CACHE_ROUND_ROBIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) bool "Round robin I and D cache replacement algorithm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) Say Y here to use the predictable round-robin cache replacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) policy. Unless you specifically require this or are unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) config CPU_BPREDICT_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) bool "Disable branch prediction"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) Say Y here to disable branch prediction. If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) config CPU_SPECTRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) select GENERIC_CPU_VULNERABILITIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) config HARDEN_BRANCH_PREDICTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) bool "Harden the branch predictor against aliasing attacks" if EXPERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) depends on CPU_SPECTRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) Speculation attacks against some high-performance processors rely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) on being able to manipulate the branch predictor for a victim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) context by executing aliasing branches in the attacker context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) Such attacks can be partially mitigated against by clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) internal branch predictor state and limiting the prediction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) logic in some situations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) This config option will take CPU-specific actions to harden
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) the branch predictor against aliasing attacks and may rely on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) specific instruction sequences or control bits being set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) the system firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) If unsure, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) config HARDEN_BRANCH_HISTORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) bool "Harden Spectre style attacks against branch history" if EXPERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) depends on CPU_SPECTRE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) Speculation attacks against some high-performance processors can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) make use of branch history to influence future speculation. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) taking an exception, a sequence of branches overwrites the branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) history, or branch history is invalidated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) config TLS_REG_EMUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) select NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) An SMP system using a pre-ARMv6 processor (there are apparently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) a few prototypes like that in existence) and therefore access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) that required register must be emulated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) config NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) config KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) depends on MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) Warning: disabling this option may break user programs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) Provide kuser helpers in the vector page. The kernel provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) helper code to userspace in read only form at a fixed location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) in the high vector page to allow userspace to be independent of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) the CPU type fitted to the system. This permits binaries to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) run on ARMv4 through to ARMv7 without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) See Documentation/arm/kernel_user_helpers.rst for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) However, the fixed address nature of these helpers can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) by ROP (return orientated programming) authors when creating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) exploits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) If all of the binaries and libraries which run on your platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) are built specifically for your platform, and make no use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) these helpers, then you can turn this option off to hinder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) such exploits. However, in that case, if a binary or library
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) relying on those helpers is run, it will receive a SIGILL signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) which will terminate the program.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) Say N here only if you are absolutely certain that you do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) need these helpers; otherwise, the safe option is to say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) config VDSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) bool "Enable VDSO for acceleration of some system calls"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) depends on AEABI && MMU && CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) default y if ARM_ARCH_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) select HAVE_GENERIC_VDSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) select GENERIC_TIME_VSYSCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) select GENERIC_VDSO_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) select GENERIC_GETTIMEOFDAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) Place in the process address space an ELF shared object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) providing fast implementations of gettimeofday and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) clock_gettime. Systems that implement the ARM architected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) timer will receive maximum benefit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) You must have glibc 2.22 or later for programs to seamlessly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) take advantage of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) config DMA_CACHE_RWFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) bool "Enable read/write for ownership DMA cache maintenance"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) depends on CPU_V6K && SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) The Snoop Control Unit on ARM11MPCore does not detect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) cache maintenance operations and the dma_{map,unmap}_area()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) functions may leave stale cache entries on other CPUs. By
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) enabling this option, Read or Write For Ownership in the ARMv6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) DMA cache maintenance functions is performed. These LDR/STR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) instructions change the cache line state to shared or modified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) so that the cache operation has the desired effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) Note that the workaround is only valid on processors that do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) not perform speculative loads into the D-cache. For such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) processors, if cache maintenance operations are not broadcast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) in hardware, other workarounds are needed (e.g. cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) maintenance broadcasting in software via FIQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) config OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) config OUTER_CACHE_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) select ARM_HEAVY_MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) The outer cache has a outer_cache_fns.sync function pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) that can be used to drain the write buffer of the outer cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) config CACHE_B15_RAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) depends on ARCH_BRCMSTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) This option enables the Broadcom Brahma-B15 read-ahead cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) controller. If disabled, the read-ahead cache remains off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) config CACHE_FEROCEON_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) bool "Enable the Feroceon L2 cache controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) depends on ARCH_MV78XX0 || ARCH_MVEBU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) select OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) This option enables the Feroceon L2 cache controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) config CACHE_FEROCEON_L2_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) bool "Force Feroceon L2 cache write through"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) depends on CACHE_FEROCEON_L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) Say Y here to use the Feroceon L2 cache in writethrough mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) Unless you specifically require this, say N for writeback mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) config MIGHT_HAVE_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) This option should be selected by machines which have a L2x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) or PL310 cache controller, but where its use is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) The only effect of this option is to make CACHE_L2X0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) related options available to the user for configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) Boards or SoCs which always require the cache controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) support to be present should select CACHE_L2X0 directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) instead of this option, thus preventing the user from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) inadvertently configuring a broken kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) config CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) default MIGHT_HAVE_CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) select OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) select OUTER_CACHE_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) This option enables the L2x0 PrimeCell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) config CACHE_L2X0_PMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) bool "L2x0 performance monitor support" if CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) depends on PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) This option enables support for the performance monitoring features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) of the L220 and PL310 outer cache controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) config PL310_ERRATA_588369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) The PL310 L2 cache controller implements three types of Clean &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) Invalidate maintenance operations: by Physical Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) They are architecturally defined to behave as the execution of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) clean operation followed immediately by an invalidate operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) both performing to the same memory location. This functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) as clean lines are not invalidated as a result of these operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) config PL310_ERRATA_727915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PL310 implements the Clean & Invalidate by Way L2 cache maintenance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) operation (offset 0x7FC). This operation runs in background so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PL310 can handle normal accesses while it is in progress. Under very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) rare circumstances, due to this erratum, write data can be lost when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PL310 treats a cacheable write transaction during a Clean &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) Invalidate by Way operation. Revisions prior to r3p1 are affected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) this errata (fixed in r3p1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) config PL310_ERRATA_753970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) bool "PL310 errata: cache sync operation may be faulty"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) This option enables the workaround for the 753970 PL310 (r3p0) erratum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) Under some condition the effect of cache sync operation on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) the store buffer still remains when the operation completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) This means that the store buffer is always asked to drain and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) this prevents it from merging any further writes. The workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) is to replace the normal offset of cache sync operation (0x730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) by another offset targeting an unmapped PL310 register 0x740.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) This has the same effect as the cache sync operation: store buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) drain and waiting for all buffers empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) config PL310_ERRATA_769419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) bool "PL310 errata: no automatic Store Buffer drain"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) On revisions of the PL310 prior to r3p2, the Store Buffer does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) not automatically drain. This can cause normal, non-cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) writes to be retained when the memory system is idle, leading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) to suboptimal I/O performance for drivers using coherent DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) This option adds a write barrier to the cpu_idle loop so that,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) on systems with an outer cache, the store buffer is drained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) explicitly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) config CACHE_TAUROS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) bool "Enable the Tauros2 L2 cache controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) depends on (CPU_MOHAWK || CPU_PJ4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) select OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) This option enables the Tauros2 L2 cache controller (as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) found on PJ1/PJ4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) config CACHE_UNIPHIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) bool "Enable the UniPhier outer cache controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) depends on ARCH_UNIPHIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) select ARM_L1_CACHE_SHIFT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) select OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) select OUTER_CACHE_SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) This option enables the UniPhier outer cache (system cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) config CACHE_XSC3L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) bool "Enable the L2 cache on XScale3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) depends on CPU_XSC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) select OUTER_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) This option enables the L2 cache on XScale3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) config ARM_L1_CACHE_SHIFT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) default y if CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) Setting ARM L1 cache line size to 64 Bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) config ARM_L1_CACHE_SHIFT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) Setting ARM L1 cache line size to 128 Bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) config ARM_L1_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) default 7 if ARM_L1_CACHE_SHIFT_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) default 6 if ARM_L1_CACHE_SHIFT_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) default 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) config ARM_DMA_MEM_BUFFERABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) Historically, the kernel has used strongly ordered mappings to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) provide DMA coherent memory. With the advent of ARMv7, mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) memory with differing types results in unpredictable behaviour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) so on these CPUs, this option is forced on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) Multiple mappings with differing attributes is also unpredictable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) on ARMv6 CPUs, but since they do not have aggressive speculative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) prefetch, no harm appears to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) However, drivers may be missing the necessary barriers for ARMv6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) and therefore turning this on may result in unpredictable driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) behaviour. Therefore, we offer this as an option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) On some of the beefier ARMv7-M machines (with DMA and write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) buffers) you likely want this enabled, while those that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) didn't need it until now also won't need it in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) You are recommended say 'Y' here and debug any affected drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) config ARM_HEAVY_MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) config ARCH_SUPPORTS_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) This option specifies the architecture can support big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) config DEBUG_ALIGN_RODATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) bool "Make rodata strictly non-executable"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) depends on STRICT_KERNEL_RWX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) If this is set, rodata will be made explicitly non-executable. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) provides protection on the rare chance that attackers might find and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) use ROP gadgets that exist in the rodata section. This adds an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) additional section-aligned split of rodata from kernel text so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) can be made explicitly non-executable. This padding may waste memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) space to gain the additional protection.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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