^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx SLCR driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011-2013 Xilinx Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/zynq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SLCR_UNLOCK_MAGIC 0xDF0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLCR_A9_CPU_CLKSTOP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLCR_A9_CPU_RST 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void __iomem *zynq_slcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct regmap *zynq_slcr_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * zynq_slcr_write - Write to a register in SLCR block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @val: Value to write to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @offset: Register offset in SLCR block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Return: a negative value on error, 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int zynq_slcr_write(u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return regmap_write(zynq_slcr_regmap, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * zynq_slcr_read - Read a register in SLCR block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @val: Pointer to value to be read from SLCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @offset: Register offset in SLCR block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Return: a negative value on error, 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int zynq_slcr_read(u32 *val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return regmap_read(zynq_slcr_regmap, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * zynq_slcr_unlock - Unlock SLCR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Return: a negative value on error, 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline int zynq_slcr_unlock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * zynq_slcr_get_device_id - Read device code id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Return: Device code id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 zynq_slcr_get_device_id(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) zynq_slcr_read(&val, SLCR_PSS_IDCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val &= SLCR_PSS_IDCODE_DEVICE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * zynq_slcr_system_restart - Restart the entire system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @nb: Pointer to restart notifier block (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @action: Reboot mode (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @data: Restart handler private data (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Return: 0 always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int zynq_slcr_system_restart(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 reboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Clear 0x0F000000 bits of reboot status register to workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * the FSBL not loading the bitstream after soft-reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * This is a temporary solution until we know more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct notifier_block zynq_slcr_restart_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .notifier_call = zynq_slcr_system_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .priority = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * zynq_slcr_cpu_start - Start cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @cpu: cpu number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void zynq_slcr_cpu_start(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg &= ~(SLCR_A9_CPU_RST << cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) zynq_slcr_cpu_state_write(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * zynq_slcr_cpu_stop - Stop cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @cpu: cpu number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void zynq_slcr_cpu_stop(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * zynq_slcr_cpu_state - Read/write cpu state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @cpu: cpu number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 0 means cpu is running, 1 cpu is going to die.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Return: true if cpu is running, false if cpu is going to die
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool zynq_slcr_cpu_state_read(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) state &= 1 << (31 - cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return !state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * zynq_slcr_cpu_state - Read/write cpu state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @cpu: cpu number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @die: cpu state - true if cpu is going to die
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * 0 means cpu is running, 1 cpu is going to die.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void zynq_slcr_cpu_state_write(int cpu, bool die)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 state, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mask = 1 << (31 - cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (die)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) state |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) state &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * zynq_early_slcr_init - Early slcr init function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Return: 0 on success, negative errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Called very early during boot from platform code to unlock SLCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int __init zynq_early_slcr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_err("%s: no slcr node found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) zynq_slcr_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!zynq_slcr_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_err("%s: Unable to map I/O memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) np->data = (__force void *)zynq_slcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (IS_ERR(zynq_slcr_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pr_err("%s: failed to find zynq-slcr\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* unlock the SLCR so that registers can be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) zynq_slcr_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* See AR#54190 design advisory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) register_restart_handler(&zynq_slcr_restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pr_info("%pOFn mapped to %p\n", np, zynq_slcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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