Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This file contains common function prototypes to avoid externs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * in the c files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Copyright (C) 2011 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __MACH_ZYNQ_COMMON_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __MACH_ZYNQ_COMMON_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extern int zynq_slcr_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern int zynq_early_slcr_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern void zynq_slcr_cpu_stop(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern void zynq_slcr_cpu_start(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern bool zynq_slcr_cpu_state_read(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern void zynq_slcr_cpu_state_write(int cpu, bool die);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) extern u32 zynq_slcr_get_device_id(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern char zynq_secondary_trampoline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern char zynq_secondary_trampoline_jump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) extern char zynq_secondary_trampoline_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) extern int zynq_cpun_start(u32 address, int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) extern const struct smp_operations zynq_smp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern void __iomem *zynq_scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void zynq_pm_late_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline void zynq_core_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	/* A9 clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		      "orr  r12, r12, #1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		      "mcr  p15, 0, r12, c15, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		      : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		      : /* no inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		      : "r12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif