^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file contains common code that is intended to be used across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * boards so that it's not replicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk/zynq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ZYNQ_DEVCFG_MCTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *zynq_scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * zynq_memory_init - Initialize special memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * We need to stop things allocating the low memory as DMA can't work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * the 1st 512K of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void __init zynq_memory_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!__pa(PAGE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) memblock_reserve(__pa(PAGE_OFFSET), 0x80000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct platform_device zynq_cpuidle_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "cpuidle-zynq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * zynq_get_revision - Get Zynq silicon revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Return: Silicon version or -1 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int __init zynq_get_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *zynq_devcfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_err("%s: no devcfg node found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) zynq_devcfg_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!zynq_devcfg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_err("%s: Unable to map I/O memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iounmap(zynq_devcfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void __init zynq_init_late(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) zynq_core_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) zynq_pm_late_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * zynq_init_machine - System specific initialization, intended to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * called from board specific initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void __init zynq_init_machine(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct soc_device_attribute *soc_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct soc_device *soc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device *parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!soc_dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) system_rev = zynq_get_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) zynq_slcr_get_device_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) soc_dev = soc_device_register(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (IS_ERR(soc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) kfree(soc_dev_attr->family);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) kfree(soc_dev_attr->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) kfree(soc_dev_attr->soc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) kfree(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) parent = soc_device_to_device(soc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Finished with the static registrations now; fill in the missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) of_platform_default_populate(NULL, NULL, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) platform_device_register(&zynq_cpuidle_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void __init zynq_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) zynq_clock_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) timer_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct map_desc zynq_cortex_a9_scu_map __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .length = SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void __init zynq_scu_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) base = scu_a9_get_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Expected address is in vmalloc area that's why simple assign here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) zynq_cortex_a9_scu_map.virtual = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) iotable_init(&zynq_cortex_a9_scu_map, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) zynq_scu_base = (void __iomem *)base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) BUG_ON(!zynq_scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * zynq_map_io - Create memory mappings needed for early I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void __init zynq_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) debug_ll_io_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) zynq_scu_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void __init zynq_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) zynq_early_slcr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char * const zynq_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "xlnx,zynq-7000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* 64KB way size, 8-way associativity, parity disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .l2c_aux_val = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .l2c_aux_mask = 0xffbfffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .smp = smp_ops(zynq_smp_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .map_io = zynq_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .init_irq = zynq_irq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .init_machine = zynq_init_machine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .init_late = zynq_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .init_time = zynq_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .dt_compat = zynq_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .reserve = zynq_memory_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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