^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Jun Nie <jun.nie@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCU_DM_CLKEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCU_DM_RSTEN 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCU_DM_ISOEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCU_DM_PWRDN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCU_DM_ACK_SYNC 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PCU_DM_NEON0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PCU_DM_NEON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PCU_DM_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PCU_DM_DECPPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PCU_DM_VOU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PCU_DM_R2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PCU_DM_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __iomem *pcubase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct zx_pm_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct generic_pm_domain dm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int normal_power_off(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long loop = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writel_relaxed(tmp, pcubase + PCU_DM_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel_relaxed(tmp, pcubase + PCU_DM_RSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } while (--loop && !tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!loop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pr_err("Error: %s %s fail\n", __func__, domain->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int normal_power_on(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long loop = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(tmp, pcubase + PCU_DM_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } while (--loop && tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!loop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pr_err("Error: %s %s fail\n", __func__, domain->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(tmp, pcubase + PCU_DM_ISOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tmp &= ~BIT(zpd->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct zx_pm_domain gpu_domain = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .dm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "gpu_domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .power_off = normal_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .power_on = normal_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .bit = PCU_DM_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct zx_pm_domain decppu_domain = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .dm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "decppu_domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .power_off = normal_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .power_on = normal_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .bit = PCU_DM_DECPPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct zx_pm_domain vou_domain = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .dm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "vou_domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .power_off = normal_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .power_on = normal_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .bit = PCU_DM_VOU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct zx_pm_domain r2d_domain = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .dm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "r2d_domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .power_off = normal_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .power_on = normal_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .bit = PCU_DM_R2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct generic_pm_domain *zx296702_pm_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &vou_domain.dm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &gpu_domain.dm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &decppu_domain.dm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &r2d_domain.dm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int zx296702_pd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct genpd_onecell_data *genpd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!genpd_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) genpd_data->domains = zx296702_pm_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) genpd_data->num_domains = ARRAY_SIZE(zx296702_pm_domains);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(&pdev->dev, "no memory resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pcubase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ERR(pcubase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(&pdev->dev, "ioremap fail.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for (i = 0; i < ARRAY_SIZE(zx296702_pm_domains); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pm_genpd_init(zx296702_pm_domains[i], NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct of_device_id zx296702_pm_domain_matches[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .compatible = "zte,zx296702-pcu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct platform_driver zx296702_pd_driver __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "zx-powerdomain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .of_match_table = zx296702_pm_domain_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .probe = zx296702_pd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int __init zx296702_pd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return platform_driver_register(&zx296702_pd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) subsys_initcall(zx296702_pd_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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