^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/fncpy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AON_SYS_CTRL_RESERVED1 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BUS_MATRIX_REMAP_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCU_CPU0_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCU_CPU1_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCU_CPU1_ST 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCU_GLOBAL_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCU_EXPEND_CONTROL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZX_IRAM_BASE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void __iomem *pcu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void __iomem *matrix_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __init zx_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *aonsysctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *sys_iram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) base = scu_a9_get_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) scu_base = ioremap(base, SZ_256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (!scu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pr_err("%s: failed to map scu\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) np = of_find_compatible_node(NULL, NULL, "zte,sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pr_err("%s: failed to find sysctrl node\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) aonsysctrl_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!aonsysctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_err("%s: failed to map aonsysctrl\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Write the address of secondary startup into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * system-wide flags register. The BootMonitor waits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * until it receives a soft interrupt, and then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * secondary CPU branches to this address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __raw_writel(__pa_symbol(zx_secondary_startup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) iounmap(aonsysctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) np = of_find_compatible_node(NULL, NULL, "zte,zx296702-pcu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pcu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) WARN_ON(!pcu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) np = of_find_compatible_node(NULL, NULL, "zte,zx-bus-matrix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) matrix_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) WARN_ON(!matrix_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Map the first 4 KB IRAM for suspend usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int zx_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static bool first_boot = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (first_boot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) first_boot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Swap the base address mapping between IRAM and IROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(0x1, matrix_base + BUS_MATRIX_REMAP_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Power on CPU1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel_relaxed(0x0, pcu_base + PCU_CPU1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Wait for power on ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) while (readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Swap back the mapping of IRAM and IROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel_relaxed(0x0, matrix_base + BUS_MATRIX_REMAP_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void cpu_enter_lowpower(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "mcr p15, 0, %1, c7, c5, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) " mcr p15, 0, %1, c7, c10, 4\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Turn off coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) " mrc p15, 0, %0, c1, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) " bic %0, %0, %3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) " mcr p15, 0, %0, c1, c0, 1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) " mrc p15, 0, %0, c1, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) " bic %0, %0, %2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) " mcr p15, 0, %0, c1, c0, 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) : "=&r" (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) : "r" (0), "Ir" (CR_C), "Ir" (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int zx_cpu_kill(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long timeout = jiffies + msecs_to_jiffies(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel_relaxed(0x2, pcu_base + PCU_CPU1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) while ((readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x3) != 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pr_err("*** cpu1 poweroff timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void zx_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) scu_power_mode(scu_base, SCU_PM_POWEROFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cpu_enter_lowpower();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) while (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void zx_secondary_init(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) scu_power_mode(scu_base, SCU_PM_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct smp_operations zx_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .smp_prepare_cpus = zx_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .smp_secondary_init = zx_secondary_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .smp_boot_secondary = zx_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .cpu_kill = zx_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .cpu_die = zx_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CPU_METHOD_OF_DECLARE(zx_smp, "zte,zx296702-smp", &zx_smp_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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