^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-vt8500/vt8500.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LEGACY_GPIO_BASE 0xD8110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LEGACY_PMC_BASE 0xD8130000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Registers in GPIO Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VT8500_GPIO_MUX_REG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Registers in Power Management Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VT8500_HCR_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VT8500_PMSR_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void vt8500_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) writel(1, pmc_base + VT8500_PMSR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct map_desc vt8500_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* SoC MMIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .virtual = 0xf8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .pfn = __phys_to_pfn(0xd8000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .length = 0x00390000, /* max of all chip variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void __init vt8500_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void vt8500_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writew(5, pmc_base + VT8500_HCR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void __init vt8500_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device_node *fb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef CONFIG_FB_VT8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) gpio_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_err("%s: of_iomap(gpio_mux) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (gpio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gpio_base + VT8500_GPIO_MUX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) iounmap(gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_err("%s: Could not remap GPIO mux\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) of_node_put(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_FB_WM8505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (fb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "wm,wm8650-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gpio_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("%s: of_iomap(gpio_mux) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (gpio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iounmap(gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pr_err("%s: Could not remap GPIO mux\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) of_node_put(fb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pmc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_err("%s:of_iomap(pmc) failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_err("%s:ioremap(power_off) failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (pmc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pm_power_off = &vt8500_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const vt8500_dt_compat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "via,vt8500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "wm,wm8650",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "wm,wm8505",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "wm,wm8750",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "wm,wm8850",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .dt_compat = vt8500_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .map_io = vt8500_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .init_machine = vt8500_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .restart = vt8500_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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