Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Created by:	Nicolas Pitre, October 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright:	(C) 2012-2013  Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Some portions of this file were originally written by Achin Gupta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright:   (C) 2012  ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/mcpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/arm-cci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "spc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* SCC conf registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RESET_CTRL		0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RESET_A15_NCORERESET(cpu)	(1 << (2 + (cpu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RESET_A7_NCORERESET(cpu)	(1 << (16 + (cpu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define A15_CONF		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define A7_CONF			0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SYS_INFO		0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SPC_BASE		0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static void __iomem *scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TC2_CLUSTERS			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TC2_MAX_CPUS_PER_CLUSTER	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int tc2_pm_cpu_powerup(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ve_spc_set_resume_addr(cluster, cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			       __pa_symbol(mcpm_entry_point));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ve_spc_cpu_wakeup_irq(cluster, cpu, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int tc2_pm_cluster_powerup(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (cluster >= TC2_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ve_spc_powerdown(cluster, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ve_spc_cpu_wakeup_irq(cluster, cpu, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * If the CPU is committed to power down, make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * the power controller will be in charge of waking it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * up upon IRQ, ie IRQ lines are cut from GIC CPU IF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * to the CPU by disabling the GIC CPU IF to prevent wfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * from completing execution behind power controller back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	gic_cpu_if_down(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	BUG_ON(cluster >= TC2_CLUSTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ve_spc_powerdown(cluster, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ve_spc_global_wakeup_irq(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void tc2_pm_cpu_cache_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	v7_exit_coherency_flush(louis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void tc2_pm_cluster_cache_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		 * On the Cortex-A15 we need to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 * L2 prefetching before flushing the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		"mcr	p15, 1, %0, c15, c0, 3 \n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		"isb	\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		"dsb	"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		: : "r" (0x400) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	v7_exit_coherency_flush(all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	cci_disable_port_by_cpu(read_cpuid_mpidr());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 mask = cluster ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		  RESET_A7_NCORERESET(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		: RESET_A15_NCORERESET(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return !(readl_relaxed(scc + RESET_CTRL) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define POLL_MSEC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TIMEOUT_MSEC 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			 __func__, cpu, cluster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			 readl_relaxed(scc + RESET_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		 * We need the CPU to reach WFI, but the power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 * controller may put the cluster in reset and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * power it off as soon as that happens, before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * we have a chance to see STANDBYWFI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		 * So we need to check for both conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (tc2_core_in_reset(cpu, cluster) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		    ve_spc_cpu_in_wfi(cpu, cluster))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			return 0; /* success: the CPU is halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		/* Otherwise, wait and retry: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		msleep(POLL_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return -ETIMEDOUT; /* timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void tc2_pm_cpu_suspend_prepare(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ve_spc_set_resume_addr(cluster, cpu, __pa_symbol(mcpm_entry_point));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void tc2_pm_cpu_is_up(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ve_spc_cpu_wakeup_irq(cluster, cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ve_spc_set_resume_addr(cluster, cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void tc2_pm_cluster_is_up(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	BUG_ON(cluster >= TC2_CLUSTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ve_spc_powerdown(cluster, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ve_spc_global_wakeup_irq(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct mcpm_platform_ops tc2_pm_power_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.cpu_powerup		= tc2_pm_cpu_powerup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.cluster_powerup	= tc2_pm_cluster_powerup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.cpu_suspend_prepare	= tc2_pm_cpu_suspend_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.cpu_powerdown_prepare	= tc2_pm_cpu_powerdown_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.cluster_powerdown_prepare = tc2_pm_cluster_powerdown_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.cpu_cache_disable	= tc2_pm_cpu_cache_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.cluster_cache_disable	= tc2_pm_cluster_cache_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.wait_for_powerdown	= tc2_pm_wait_for_powerdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.cpu_is_up		= tc2_pm_cpu_is_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.cluster_is_up		= tc2_pm_cluster_is_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * Enable cluster-level coherency, in preparation for turning on the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	asm volatile (" \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "	cmp	r0, #1 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "	bxne	lr \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "	b	cci_enable_port_for_self ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int __init tc2_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned int mpidr, cpu, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32 a15_cluster_id, a7_cluster_id, sys_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * The power management-related features are hidden behind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * SCC registers. We need to extract runtime information like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * cluster ids and number of CPUs really available in clusters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			"arm,vexpress-scc,v2p-ca15_a7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	scc = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!scc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	sys_info = readl_relaxed(scc + SYS_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * A subset of the SCC registers is also used to communicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * with the SPC (power controller). We need to be able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * drive it very early in the boot process to power up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * processors, so we initialize the SPC driver here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (!cci_probed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	mpidr = read_cpuid_mpidr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		pr_err("%s: boot CPU is out of bound!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ret = mcpm_platform_register(&tc2_pm_power_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		mcpm_sync_init(tc2_pm_power_up_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		/* test if we can (re)enable the CCI on our own */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		pr_info("TC2 power management initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) early_initcall(tc2_pm_init);