^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Versatile Express Serial Power Controller (SPC) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Achin Gupta <achin.gupta@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/semaphore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "spc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPCLOG "vexpress-spc: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PERF_LVL_A15 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PERF_REQ_A15 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PERF_LVL_A7 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PERF_REQ_A7 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define COMMS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define COMMS_REQ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWC_STATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PWC_FLAG 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SPC wake-up IRQs status and mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WAKE_INT_MASK 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WAKE_INT_RAW 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WAKE_INT_STAT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* SPC power down registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define A15_PWRDN_EN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define A7_PWRDN_EN 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* SPC per-CPU mailboxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define A15_BX_ADDR0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define A7_BX_ADDR0 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* SPC CPU/cluster reset statue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STANDBYWFI_STAT 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* SPC system config interface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SYSCFG_WDATA 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SYSCFG_RDATA 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* A15/A7 OPP virtual register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define A15_PERFVAL_BASE 0xC10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define A7_PERFVAL_BASE 0xC30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Config interface control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SYSCFG_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SYSCFG_SCC (6 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SYSCFG_STAT (14 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* wake-up interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GBL_WAKEUP_INT_MSK (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* TC2 static dual-cluster configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX_CLUSTERS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * operation, the operation could start just before jiffie is about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * to be incremented. So setting timeout value of 20ms = 2jiffies@100Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TIMEOUT_US 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAX_OPPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CA15_DVFS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CA7_DVFS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPC_SYS_CFG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STAT_ERR(type) ((1 << 1) << (type << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct ve_spc_opp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long u_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct ve_spc_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __iomem *baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * A15s cluster identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * It corresponds to A15 processors MPIDR[15:8] bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 a15_clusid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) uint32_t cur_rsp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) uint32_t cur_rsp_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct semaphore sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ve_spc_opp *opps[MAX_CLUSTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int num_opps[MAX_CLUSTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct ve_spc_drvdata *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline bool cluster_is_a15(u32 cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return cluster == info->a15_clusid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * ve_spc_global_wakeup_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Function to set/clear global wakeup IRQs. Not protected by locking since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * it might be used in code paths where normal cacheable locks are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * working. Locking must be provided by the caller to ensure atomicity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @set: if true, global wake-up IRQs are set, if false they are cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void ve_spc_global_wakeup_irq(bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reg |= GBL_WAKEUP_INT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg &= ~GBL_WAKEUP_INT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * ve_spc_cpu_wakeup_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * it might be used in code paths where normal cacheable locks are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * working. Locking must be provided by the caller to ensure atomicity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @cluster: mpidr[15:8] bitfield describing cluster affinity level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @cpu: mpidr[7:0] bitfield describing cpu affinity level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @set: if true, wake-up IRQs are set, if false they are cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 mask, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (cluster >= MAX_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mask = BIT(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!cluster_is_a15(cluster))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mask <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * ve_spc_set_resume_addr() - set the jump address used for warm boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @cluster: mpidr[15:8] bitfield describing cluster affinity level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @cpu: mpidr[7:0] bitfield describing cpu affinity level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @addr: physical resume address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void __iomem *baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (cluster >= MAX_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (cluster_is_a15(cluster))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(addr, baseaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * ve_spc_powerdown()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Function to enable/disable cluster powerdown. Not protected by locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * since it might be used in code paths where normal cacheable locks are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * working. Locking must be provided by the caller to ensure atomicity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @cluster: mpidr[15:8] bitfield describing cluster affinity level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @enable: if true enables powerdown, if false disables it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void ve_spc_powerdown(u32 cluster, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 pwdrn_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (cluster >= MAX_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel_relaxed(enable, info->baseaddr + pwdrn_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return cluster_is_a15(cluster) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) STANDBYWFI_STAT_A15_CPU_MASK(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) : STANDBYWFI_STAT_A7_CPU_MASK(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @cluster: mpidr[15:8] bitfield describing cluster affinity level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @return: non-zero if and only if the specified CPU is in WFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Take care when interpreting the result of this function: a CPU might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * be in WFI temporarily due to idle, and is not necessarily safely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * parked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 mask = standbywfi_cpu_mask(cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (cluster >= MAX_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __func__, STANDBYWFI_STAT, ret, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int ve_spc_get_performance(int cluster, u32 *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ve_spc_opp *opps = info->opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 perf_cfg_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) perf_cfg_reg = cluster_is_a15(cluster) ? PERF_LVL_A15 : PERF_LVL_A7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) perf = readl_relaxed(info->baseaddr + perf_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (perf >= info->num_opps[cluster])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) opps += perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *freq = opps->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* find closest match to given frequency in OPP table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int ve_spc_round_performance(int cluster, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int idx, max_opp = info->num_opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct ve_spc_opp *opps = info->opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 fmin = 0, fmax = ~0, ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) freq /= 1000; /* OPP entries in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) for (idx = 0; idx < max_opp; idx++, opps++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ftmp = opps->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ftmp >= freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ftmp <= fmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) fmax = ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ftmp >= fmin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) fmin = ftmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (fmax != ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return fmax * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return fmin * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int ve_spc_find_performance_index(int cluster, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int idx, max_opp = info->num_opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ve_spc_opp *opps = info->opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for (idx = 0; idx < max_opp; idx++, opps++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (opps->freq == freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return (idx == max_opp) ? -EINVAL : idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int ve_spc_waitforcompletion(int req_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int ret = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) &info->done, usecs_to_jiffies(TIMEOUT_US));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = info->cur_rsp_stat & STAT_COMPLETE(req_type) ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int ve_spc_set_performance(int cluster, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 perf_cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret, perf, req_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (cluster_is_a15(cluster)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) req_type = CA15_DVFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) perf_cfg_reg = PERF_LVL_A15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) req_type = CA7_DVFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) perf_cfg_reg = PERF_LVL_A7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) perf = ve_spc_find_performance_index(cluster, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (perf < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return perf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) init_completion(&info->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) info->cur_rsp_mask = RESPONSE_MASK(req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writel(perf, info->baseaddr + perf_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = ve_spc_waitforcompletion(req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) info->cur_rsp_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) up(&info->sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int ve_spc_read_sys_cfg(int func, int offset, uint32_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (down_timeout(&info->sem, usecs_to_jiffies(TIMEOUT_US)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) init_completion(&info->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) info->cur_rsp_mask = RESPONSE_MASK(SPC_SYS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Set the control value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(SYSCFG_START | func | offset >> 2, info->baseaddr + COMMS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = ve_spc_waitforcompletion(SPC_SYS_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *data = readl(info->baseaddr + SYSCFG_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) info->cur_rsp_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) up(&info->sem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static irqreturn_t ve_spc_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ve_spc_drvdata *drv_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (info->cur_rsp_mask & status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) info->cur_rsp_stat = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) complete(&drv_data->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * +--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * | 31 20 | 19 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * +--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * | m_volt | freq(kHz) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * +--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MULT_FACTOR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define VOLT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define FREQ_MASK (0xFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int ve_spc_populate_opps(uint32_t cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) uint32_t data = 0, off, ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct ve_spc_opp *opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) opps = kcalloc(MAX_OPPS, sizeof(*opps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!opps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) info->opps[cluster] = opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) off = cluster_is_a15(cluster) ? A15_PERFVAL_BASE : A7_PERFVAL_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (idx = 0; idx < MAX_OPPS; idx++, off += 4, opps++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) opps->u_volt = (data >> VOLT_SHIFT) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) info->num_opps[cluster] = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int ve_init_opp_table(struct device *cpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int idx, ret = 0, max_opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct ve_spc_opp *opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cluster = topology_physical_package_id(cpu_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cluster = cluster < 0 ? 0 : cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) max_opp = info->num_opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) opps = info->opps[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (idx = 0; idx < max_opp; idx++, opps++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_warn(cpu_dev, "failed to add opp %lu %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) opps->freq, opps->u_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) info = kzalloc(sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) info->baseaddr = baseaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) info->a15_clusid = a15_clusid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pr_err(SPCLOG "Invalid IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) init_completion(&info->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) readl_relaxed(info->baseaddr + PWC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = request_irq(irq, ve_spc_irq_handler, IRQF_TRIGGER_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) | IRQF_ONESHOT, "vexpress-spc", info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pr_err(SPCLOG "IRQ %d request failed\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sema_init(&info->sem, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Multi-cluster systems may need this data when non-coherent, during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * cluster power-up/power-down. Make sure driver info reaches main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sync_cache_w(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) sync_cache_w(&info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct clk_spc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static unsigned long spc_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk_spc *spc = to_clk_spc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ve_spc_get_performance(spc->cluster, &freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct clk_spc *spc = to_clk_spc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ve_spc_round_performance(spc->cluster, drate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct clk_spc *spc = to_clk_spc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ve_spc_set_performance(spc->cluster, rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct clk_ops clk_spc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .recalc_rate = spc_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .round_rate = spc_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .set_rate = spc_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct clk *ve_spc_clk_register(struct device *cpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct clk_spc *spc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) spc = kzalloc(sizeof(*spc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!spc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) spc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spc->cluster = topology_physical_package_id(cpu_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) init.name = dev_name(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) init.ops = &clk_spc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) init.flags = CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return devm_clk_register(cpu_dev, &spc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int __init ve_spc_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int cpu, cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bool init_opp_table[MAX_CLUSTERS] = { false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0; /* Continue only if SPC is initialised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ve_spc_populate_opps(0) || ve_spc_populate_opps(1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pr_err("failed to build OPP table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct device *cpu_dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!cpu_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pr_warn("failed to get cpu%d device\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) clk = ve_spc_clk_register(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pr_warn("failed to register cpu%d clock\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pr_warn("failed to register cpu%d clock lookup\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) cluster = topology_physical_package_id(cpu_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (init_opp_table[cluster])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ve_init_opp_table(cpu_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pr_warn("failed to initialise cpu%d opp table\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else if (dev_pm_opp_set_sharing_cpus(cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) topology_core_cpumask(cpu_dev->id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pr_warn("failed to mark OPPs shared for cpu%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) init_opp_table[cluster] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) platform_device_register_simple("vexpress-spc-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) device_initcall(ve_spc_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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