^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Created by: Nicolas Pitre, May 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright: (C) 2012-2013 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/vexpress.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/arm-cci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mcpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RST_HOLD0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RST_HOLD1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SYS_SWRESET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RST_STAT0 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RST_STAT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EAG_CFG_R 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EAG_CFG_W 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define KFC_CFG_R 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define KFC_CFG_W 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DCS_CFG_R 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void __iomem *dcscb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int dcscb_allcpus_mask[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int rst_hold, cpumask = (1 << cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rst_hold &= ~(cpumask | (cpumask << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int dcscb_cluster_powerup(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int rst_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (cluster >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* remove cluster reset and add individual CPU's reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) rst_hold &= ~(1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rst_hold |= dcscb_allcpus_mask[cluster];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int rst_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) rst_hold |= (1 << cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void dcscb_cluster_powerdown_prepare(unsigned int cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int rst_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_debug("%s: cluster %u\n", __func__, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BUG_ON(cluster >= 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) rst_hold |= (1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void dcscb_cpu_cache_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Disable and flush the local CPU cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) v7_exit_coherency_flush(louis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void dcscb_cluster_cache_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Flush all cache levels for this cluster. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) v7_exit_coherency_flush(all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * A full outer cache flush could be needed at this point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * on platforms with such a cache, depending on where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * outer cache sits. In some cases the notion of a "last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * cluster standing" would need to be implemented if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * outer cache is shared across clusters. In any case, when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * the outer cache needs flushing, there is no concurrent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * access to the cache controller to worry about and no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * special locking besides what is already provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * MCPM state machinery is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Disable cluster-level coherency by masking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * incoming snoops and DVM messages:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) cci_disable_port_by_cpu(read_cpuid_mpidr());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct mcpm_platform_ops dcscb_power_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .cpu_powerup = dcscb_cpu_powerup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .cluster_powerup = dcscb_cluster_powerup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .cpu_cache_disable = dcscb_cpu_cache_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .cluster_cache_disable = dcscb_cluster_cache_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) extern void dcscb_power_up_setup(unsigned int affinity_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init dcscb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!cci_probed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dcscb_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!dcscb_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EADDRNOTAVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = mcpm_platform_register(&dcscb_power_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = mcpm_sync_init(dcscb_power_up_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) iounmap(dcscb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_info("VExpress DCSCB support installed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Future entries into the kernel can now go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * through the cluster entry vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) vexpress_flags_set(__pa_symbol(mcpm_entry_point));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) early_initcall(dcscb_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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